CY7C1021BNL-15ZXI Cypress Semiconductor Corp, CY7C1021BNL-15ZXI Datasheet - Page 6

• Manufacturer Part Number: CY7C1021BNL-15ZXI
• Description: IC SRAM 1MBIT 15NS 44TSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C1021BNL-15ZXI

• Memory Size: 1M (64K x 16)
• Package / Case: 44-TSOP II
• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Speed: 15ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 15 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 130 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Switching Characteristics
Document #: 001-06494 Rev. *C
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
Notes
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
SD
HD
LZWE
HZWE
BW
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I
6. At any temperature and voltage condition, t
7. t
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE / BLE LOW. CE, WE, and BHE / BLE must be LOW to initiate a write,
Parameter
and 30 pF load capacitance.
and the transition of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates
the write.
HZOE
, t
HZBE
[8]
, t
HZCE
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to low Z
OE HIGH to high Z
CE LOW to low Z
CE HIGH to high Z
CE LOW to power up
CE HIGH to power down
Byte enable to data valid
Byte enable to low Z
Byte disable to high Z
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
Data setup to write end
Data hold from write end
WE HIGH to low Z
WE LOW to high Z
Byte enable to write end
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
Description
[6]
[5]
[6]
[6, 7]
[6, 7]
[6, 7]
[5]
HZCE
[6]
[6, 7]
Over the operating range
is less than t
LZCE
, t
HZOE
CY7C10211B-10
Min
is less than t
10
10
3
0
3
0
0
8
7
0
0
5
0
3
7
-
-
-
-
-
-
-
-
-
Max
LZOE
10
10
10
5
5
5
5
5
5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
, t
HZBE
CY7C1021B-12
is less than t
Min
12
12
3
0
3
0
0
9
8
0
0
6
0
3
8
CY7C1021BN, CY7C10211BN
-
-
-
-
-
-
-
-
-
LZBE
Max
12
12
12
6
6
6
6
6
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
, and t
HZWE
CY7C1021B-15
Min
15
15
10
10
3
0
3
0
0
0
0
8
0
3
9
-
-
-
-
-
-
-
-
-
is less than t
Max
15
15
15
7
7
7
7
7
7
-
LZWE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Page 6 of 13
for any device.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OL
/I
OH
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