W9751G6JB-25 Winbond Electronics, W9751G6JB-25 Datasheet - Page 20

• Manufacturer Part Number: W9751G6JB-25
• Description: IC DDR2-800 SDRAM 512MB 84WBGA
• Manufacturer: Winbond Electronics

Specifications of W9751G6JB-25

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (32Mx16)
• Speed: 2.5ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 84-WBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5606783

7.3
7.3.1
( CS = "L", RAS = "L", CAS = "H", WE = "H", BA0, BA1 = Bank, A0 to A12 be row address)
The Bank Activate command must be applied before any Read or Write operation can be executed.
Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command
on the following clock cycle. If a Read/Write command is issued to a bank that has not satisfied the
t
Read/Write command is internally issued to the device. The additive latency value must be chosen to
assure t
been activated it must be precharged before another Bank Activate command can be applied to the
same bank. The bank active and precharge times are defined as t
minimum time interval between successive Bank Activate commands to the same bank is determined
by the RAS cycle time of the device (t
commands is t
7.3.2
( CS = "L", RAS = "H", CAS = "L", WE = "H", BA0, BA1 = Bank, A10 = "L", A0 to A9 = Column
Address)
The READ command is used to initiate a burst read access to an active row. The value on BA0, BA1
inputs selects the bank, and the A0 to A9 address inputs determine the starting column address. The
address input A10 determines whether or not Auto-precharge is used. If Auto-precharge is selected,
the row being accessed will be precharged at the end of the READ burst; if Auto-precharge is not
selected, the row will remain open for subsequent accesses.
RCDmin
Figure 12 – Bank activate command cycle: t
Command Function
Bank Activate Command
Read Command
RCDmin
specification, then additive latency must be programmed into the device to delay when the
RRD
is satisfied. Additive latencies of 0, 1, 2, 3, 4, 5 and 6 are supported. Once a bank has
.
RC
). The minimum time interval between Bank Activate
- 20 -
RCD
= 3, AL = 2, t
Publication Release Date: Aug. 03, 2010
RAS
RP
= 3, t
and t
RRD
W9751G6JB
RP
, respectively. The
= 2, t
CCD
Revision A04
= 2