CY62146ELL-45ZSXI Cypress Semiconductor Corp, CY62146ELL-45ZSXI Datasheet - Page 6

• Manufacturer Part Number: CY62146ELL-45ZSXI
• Description: IC SRAM 4MBIT 45NS 44TSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62146ELL-45ZSXI

• Memory Size: 4M (256K x 16)
• Package / Case: 44-TSOP II
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 45ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 45 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Current: 20 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 5 V
• Density: 4Mb
• Access Time (max): 45ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 18b
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Supply Current: 20mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Word Size: 16b
• Number Of Words: 256K
• Memory Configuration: 256K X 16
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: TSOP
• No. Of Pins: 44
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2070; CY62146ELL-45ZSXI

Switching Characteristics
Over the Operating Range
Document Number: 001-07970 Rev. *G
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
Notes
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
BW
SD
HD
HZWE
LZWE
13. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1 V/ns) or less, timing reference levels of 1.5 V, input pulse
14. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See
15. At any temperature and voltage condition, t
16. t
17. The internal write time of the memory is defined by the overlap of WE, CE = V
Parameter
levels of 0 to 3 V, and output loading of the specified I
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
HZOE
, t
HZCE
[13, 14]
[17]
, t
HZBE
, and t
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to LOW Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to power-up
CE HIGH to power-down
BLE/BHE LOW to data valid
BLE/BHE LOW to Low Z
BLE/BHE HIGH to HIGH Z
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
BLE/BHE LOW to write end
Data setup to write end
Data hold from write end
WE LOW to High Z
WE HIGH to Low Z
HZWE
transitions are measured when the outputs enter a high-impedance state.
[15]
HZCE
[15, 16]
[15, 16]
[15]
[15]
[15, 16]
is less than t
[15]
OL
[15, 16]
Description
/I
OH
as shown in
LZCE
, t
HZBE
AC Test Loads and Waveforms on page
is less than t
IL
, BHE, BLE or both = V
LZBE
, t
HZOE
is less than t
IL
. All signals must be active to initiate a write and any of these
45 ns (Ind’l/Auto-A)
LZOE
application note AN13842
Min
45
10
10
45
35
35
35
35
25
10
–
–
–
5
–
–
0
–
–
5
–
0
0
0
–
5.
, and t
HZWE
CY62146E MoBL
is less than t
Max
45
45
22
18
18
45
22
18
18
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
for further clarification.
LZWE
for any device.
Page 6 of 14
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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