CY62167DV30LL-55BVXI Cypress Semiconductor Corp, CY62167DV30LL-55BVXI Datasheet - Page 9

• Manufacturer Part Number: CY62167DV30LL-55BVXI
• Description: IC SRAM 16MBIT 55NS 48VFBGA
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY62167DV30LL-55BVXI

• Memory Size: 16M (1M x 16)
• Package / Case: 48-VFBGA
• Format - Memory: RAM
• Memory Type: SRAM
• Speed: 55ns
• Interface: Parallel
• Voltage - Supply: 2.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 55 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.2 V
• Maximum Operating Current: 30 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 2.5 V, 3.3 V
• Density: 16Mb
• Access Time (max): 55ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3V
• Address Bus: 20b
• Package Type: BGA
• Operating Temp Range: -40C to 85C
• Supply Current: 30mA
• Operating Supply Voltage (min): 2.2V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Word Size: 16b
• Number Of Words: 1M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2041; CY62167DV30LL-55BVXI

Switching Waveforms
Document Number : 38-05328 Rev. *I
ADDRESS
Notes
26. The internal Write time of the memory is defined by the overlap of WE, CE
27. Data I/O is high-impedance if OE = V
28. If CE
29. During this period, the I/Os are in output state and input signals should not be applied.
DATA I/O
ADDRESS
BHE
BHE/BLE
DATA I/O
a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the Write.
CE
/BLE
1
CE
WE
CE
CE
goes HIGH and CE
WE
OE
2
1
2
1
Note 29
Note 29
2
goes LOW simultaneously with WE = V
t
SA
(continued)
IH
Figure 5. Write Cycle 2 (CE
t
HZOE
Figure 6. Write Cycle 3 (WE Controlled, OE LOW)
t
HZWE
t
SA
t
AW
t
AW
IH
, the output remains in a high-impedance state.
t
t
BW
SCE
1
t
= V
WC
t
WC
1
t
PWE
IL
t
or CE
, BHE and/or BLE = V
BW
VALID DATA
t
t
PWE
SD
2
Controlled)
t
SCE
VALID DATA
t
SD
IL
, and CE
[26, 27, 28]
[28]
2
= V
IH
CY62167DV30 MoBL
t
HA
. All signals must be ACTIVE to initiate
t
t
HA
LZWE
t
HD
t
HD
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