CY7C1354CV25-166AXC Cypress Semiconductor Corp, CY7C1354CV25-166AXC Datasheet - Page 14
![IC SRAM 9MBIT 166MHZ 100LQFP](/photos/6/76/67624/428-100-tqfp_14x20x1_4_sml.jpg)
CY7C1354CV25-166AXC
Manufacturer Part Number
CY7C1354CV25-166AXC
Description
IC SRAM 9MBIT 166MHZ 100LQFP
Manufacturer
Cypress Semiconductor Corp
Type
Synchronousr
Datasheet
1.CY7C1354CV25-200AXC.pdf
(30 pages)
Specifications of CY7C1354CV25-166AXC
Memory Size
9M (256K x 36)
Package / Case
100-LQFP
Format - Memory
RAM
Memory Type
SRAM - Synchronous
Speed
166MHz
Interface
Parallel
Voltage - Supply
2.375 V ~ 2.625 V
Operating Temperature
0°C ~ 70°C
Access Time
3.5 ns
Maximum Clock Frequency
166 MHz
Supply Voltage (max)
2.625 V
Supply Voltage (min)
2.375 V
Maximum Operating Current
180 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Ports
4
Operating Supply Voltage
2.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-2121
CY7C1354CV25-166AXC
CY7C1354CV25-166AXC
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1354CV25-166AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C1354CV25-166AXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
TAP Timing
TAP AC Switching Characteristics
Over the Operating Range
Document Number: 38-05537 Rev. *K
Clock
t
t
t
t
Output Times
t
t
Set-up Times
t
t
t
Hold Times
t
t
t
Notes
Parameter
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
14. t
15. Test conditions are specified using the load in TAP AC test Conditions. t
CS
and t
CH
refer to the set-up and hold time requirements of latching data from the boundary scan register.
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
TMS set-up to TCK clock rise
TDI set-up to TCK clock rise
Capture set-up to TCK rise
TMS hold after TCK clock rise
TDI hold after clock rise
Capture hold after clock rise
Test Mode Select
Test Data-Out
Test Data-In
Test Clock
(TDO)
(TMS)
(TCK)
[14, 15]
(TDI)
1
Description
t TMSS
t TDIS
2
t TMSH
t TDIH
t TH
DON’T CARE
R
/t
t
F
TL
= 1 ns.
3
t CYC
UNDEFINED
4
t TDOX
t TDOV
5
Min
50
20
20
–
–
0
5
5
5
5
5
5
6
CY7C1354CV25
CY7C1356CV25
Max
20
10
–
–
–
–
–
–
–
–
–
–
Page 14 of 30
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[+] Feedback