CY7C1370D-167AXC Cypress Semiconductor Corp, CY7C1370D-167AXC Datasheet - Page 16

• Manufacturer Part Number: CY7C1370D-167AXC
• Description: IC SRAM 18MBIT 167MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1370D-167AXC

• Memory Size: 18M (512K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 3.4 ns
• Maximum Clock Frequency: 167 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 275 mA
• Organization: 128 K x 16
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Memory Configuration: 1M X 18 / 512K X 36
• Clock Frequency: 167MHz
• Supply Voltage Range: 3.135V To 3.6V
• Memory Case Style: TQFP
• No. Of Pins: 100
• Rohs Compliant: Yes
• Density: 18Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 167MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 275mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2135; CY7C1370D-167AXC

Identification Register Definitions
Scan Register Sizes
Identification Codes
Document Number: 38-05555 Rev. *K
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
Instruction
Bypass
ID
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball FBGA package)
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Note
12. Bit #24 is “1” in the Register Definitions for both 2.5Vand 3.3V versions of this device.
Instruction
Instruction Field
Register Name
Code
000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
011
100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
101 Do Not Use: This instruction is reserved for future use.
110
111
[12]
Forces all SRAM outputs to High-Z state.
operation does not affect SRAM operations.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Does not affect SRAM operation.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM opera-
tions.
01011001000100101
00000110100
CY7C1372D
000
1
01011001000010101 Reserved for future use.
Bit Size (x18)
00000110100
CY7C1370D
85
32
89
3
1
000
1
Description
Reserved for version number.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
CY7C1370D, CY7C1372D
Bit Size (x36)
Description
32
85
89
3
1
Page 16 of 29
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