CY7C1061DV33-10ZSXI Cypress Semiconductor Corp, CY7C1061DV33-10ZSXI Datasheet - Page 8

• Manufacturer Part Number: CY7C1061DV33-10ZSXI
• Description: IC SRAM 16MBIT 10NS 54TSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Asynchronousr

Specifications of CY7C1061DV33-10ZSXI

• Memory Size: 16M (1M x 16)
• Package / Case: 54-TSOP II
• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Speed: 10ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 10 ns
• Supply Voltage (max): 4.6 V
• Supply Voltage (min): 2 V
• Maximum Operating Current: 175 mA
• Organization: 1 M x 16
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 1
• Operating Supply Voltage: 3.3 V
• Density: 16Mb
• Access Time (max): 10ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 20b
• Package Type: TSOP-II
• Operating Temp Range: -40C to 85C
• Supply Current: 175mA
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 54
• Word Size: 16b
• Number Of Words: 1M
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2960-5; CY7C1061DV33-10ZSXI

AC Switching Characteristics
Over the Operating Range
Notes
Document Number: 38-05476 Rev. *G
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
t
8. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use
9. t
10. t
11. These parameters are guaranteed by design and are not tested.
12. The internal write time of the memory is defined by the overlap of WE, CE
13. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of t
power
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
BW
output loading shown in part a) of
from steady state voltage.
to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that
terminates the write.
POWER
HZOE
, t
Parameter
HZCE
gives the minimum amount of time that the power supply is at typical V
, t
[12, 13]
HZWE
, t
HZBE
, t
LZOE
[8]
, t
AC Test Loads and
V
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE
CE
CE
CE
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
Write Cycle Time
CE
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
Byte Enable to End of Write
LZCE
CC
1
1
1
1
1
1
, t
(Typical) to the First Access
LOW/CE
LOW/CE
HIGH/CE
LOW/CE
HIGH/CE
LOW/CE
LZWE
, and t
LZBE
Waveforms[7], unless specified otherwise.
2
2
2
2
2
2
HIGH to Data Valid
HIGH to Low Z
HIGH to Power Up
HIGH to Write End
LOW to High Z
LOW to Power Down
are specified with a load capacitance of 5 pF as in (b) of
[10]
[10]
[10]
Description
[10]
[10]
[9]
1
= V
[11]
IL
CC
, and CE
[11]
values until the first memory access is performed.
2
= V
IH
HZWE
. Chip enables must be active and WE and byte enables must be LOW
and t
AC Test Loads and
SD
.
Min
100
5.5
10
10
–
1
7
–
3
–
1
–
3
–
0
–
–
–
7
7
0
0
7
0
3
–
Waveforms[7]. Transition is measured 200 mV
–10
CY7C1061DV33
Max
10
10
10
–
–
–
5
–
5
–
5
–
5
–
5
–
–
–
–
–
–
–
–
–
5
–
Page 8 of 17
Unit
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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