CY7C09389V-9AXI Cypress Semiconductor Corp, CY7C09389V-9AXI Datasheet - Page 7
![IC SRAM 1.152MBIT 9NS 100LQFP](/photos/6/70/67051/428-100-tqfp_14x14x1_4_sml.jpg)
CY7C09389V-9AXI
Manufacturer Part Number
CY7C09389V-9AXI
Description
IC SRAM 1.152MBIT 9NS 100LQFP
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C09389V-9AXI.pdf
(19 pages)
Specifications of CY7C09389V-9AXI
Format - Memory
RAM
Memory Type
SRAM - Dual Port, Synchronous
Memory Size
1.152M (64K x 18)
Speed
9ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C09389V-9AXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
135
Company:
Part Number:
CY7C09389V-9AXI
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Characteristics
Over the Operating Range
Notes
Document #: 38-06056 Rev. *C
15. Test conditions used are Load 2.
16. This parameter is guaranteed by design, but it is not production tested.
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MAX1
MAX2
CYC1
CYC2
CH1
CL1
CH2
CL2
R
F
SA
HA
SC
HC
SW
HW
SD
HD
SAD
HAD
SCN
HCN
SRST
HRST
OE
OLZ
OHZ
CD1
CD2
DC
CKZ
CKZ
CWDD
CCS
Port to Port Delays
Parameter
[15,16]
[15,16]
[15,16]
[15,16]
f
f
Clock Cycle Time - Flow Through
Clock Cycle Time - Pipelined
Clock HIGH Time - Flow Through
Clock LOW Time - Flow Through
Clock HIGH Time - Pipelined
Clock LOW Time - Pipelined
Clock Rise Time
Clock Fall Time
Address Set-Up Time
Address Hold Time
Chip Enable Setup Time
Chip Enable Hold Time
R/W Set-Up Time
R/W Hold Time
Input Data Setup Time
Input Data Hold Time
ADS Set-Up Time
ADS Hold Time
CNTEN Setup Time
CNTEN Hold Time
CNTRST Setup Time
CNTRST Hold Time
Output Enable to Data Valid
OE to Low Z
OE to High Z
Clock to Data Valid - Flow Through
Clock to Data Valid - Pipelined
Data Output Hold After Clock HIGH
Clock HIGH to Output High Z
Clock HIGH to Output Low Z
Write Port Clock HIGH to Read Data Delay
Clock to Clock Setup Time
Max
Max
Flow Through
Pipelined
Description
Min
6.5
6.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
19
10
4
4
0
0
0
0
0
0
0
2
1
2
2
2
-6
[1, 2]
Max
100
6.5
53
15
30
3
3
8
7
9
9
Min
7.5
7.5
4.5
22
12
5
5
4
0
4
0
4
0
4
0
4
0
0
4
0
2
1
2
2
2
CY7C09269V/79V/89V
CY7C09369V/79V/89V
-7
[2]
Max
7.5
45
83
18
35
10
3
3
9
7
9
CY7C09269V/79V/89V
CY7C09369V/79V/89V
Min
25
15
12
12
6
6
4
1
4
1
4
1
4
1
4
1
5
1
4
1
2
1
2
2
2
-9
Max
67
40
10
20
40
15
3
3
7
9
9
Min
30
20
12
12
8
2
8
4
1
4
1
4
1
4
1
4
1
5
1
4
1
2
1
2
2
-12
Max
33
50
12
25
12
40
15
Page 7 of 19
3
3
7
9
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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