CY7C057V-12AC Cypress Semiconductor Corp, CY7C057V-12AC Datasheet - Page 17

• Manufacturer Part Number: CY7C057V-12AC
• Description: IC SRAM 32KX36 3.3V ASYN 144LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C057V-12AC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 1.152M (32K x 36)
• Speed: 12ns
• Interface: Parallel
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1173

Architecture
The CY7C056V and CY7C057V consist of an array of 16K and
32K words of 36 bits each of dual-port RAM cells, I/O and
address lines, and control signals (CE
control pins permit independent access for reads or writes to any lo-
cation in memory. To handle simultaneous writes/reads to the same
location, a BUSY pin is provided on each port. Two Interrupt (INT)
pins can be utilized for port-to-port communication. Two
Semaphore (SEM) control pins are used for allocating shared
resources. With the M/S pin, the devices can function as a
master (BUSY pins are outputs) or as a slave (BUSY pins are
inputs). The devices also have an automatic power-down fea-
ture controlled by CE
Output Enable control (OE), which allows data to be read from
the device.
Functional Description
Write Operation
Data must be set up for a duration of t
of R/W in order to guarantee a valid write. A write operation is con-
trolled by either the R/W pin (see Write Cycle No. 1 waveform) or the
CE
for non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output; other-
wise the data read is not deterministic. Data will be valid on the
port t
Read Operation
When reading the device, the user must assert both the OE
and CE
is asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE
be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (3FFF for the
CY7C056V, 7FFF for the CY7C057V) is the mailbox for the
right port and the second-highest memory location (3FFE for
the CY7C056V, 7FFE for the CY7C057V) is the mailbox for the
left port. When one port writes to the other port’s mailbox, an
interrupt is generated to the owner. The interrupt is reset when
the owner reads the contents of the mailbox. The message is
user defined.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
Document #: 38-06055 Rev. **
0
and CE
DDD
[3]
after the data is presented on the other port.
pins. Data will be available t
1
pins (see Write Cycle No. 2 waveform). Required inputs
0
/CE
1
. Each port is provided with its own
ACE
after CE or t
SD
0
[3]
/CE
before the rising edge
pin, and OE must also
1
, OE, R/W). These
DOE
after OE
Busy
The CY7C056V and CY7C057V provide on-chip arbitration to
resolve simultaneous memory location access (contention). If
both ports’ Chip Enables
occurs within t
port has access. If t
sion to the location, but it is not predictable which port will get that
permission. BUSY will be asserted t
t
Master/Slave
A M/S pin is provided in order to expand the word width by configuring
the device as either a master or a slave. The BUSY output of the
master is connected to the BUSY input of the slave. This will allow the
device to interface to a master device with no external components.
Writing to slave devices must be delayed until after the BUSY input
has settled (t
cycle during a contention situation. When tied HIGH, the M/S pin al-
lows the device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration outcome
to a slave.
Semaphore Operation
The CY7C056V and CY7C057V provide eight semaphore
latches, which are separate from the dual-port memory loca-
tions. Semaphores are used to reserve resources that are
shared between the two ports. The state of the semaphore
indicates that a resource is in use. For example, if the left port
wants to request a given resource, it sets a latch by writing a
zero to a semaphore location. The left port then verifies its
success in setting the latch by reading it. After writing to the
semaphore, SEM or OE must be deasserted for t
tempting to read the semaphore. The semaphore value will be avail-
able t
left port was successful (reads a 0), it assumes control of the shared
resource, otherwise (reads a 1) it assumes the right port has control
and continues to poll the semaphore. When the right side has relin-
quished control of the semaphore (by writing a 1), the left side will
succeed in gaining control of the semaphore. If the left side no longer
requires the semaphore, a one is written to cancel its request.
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches. For normal
semaphore access, CE
CE active semaphore access is also available. The semaphore may
be accessed through the right port with CE
ing the Bus Match Select (BM) pin LOW and asserting the Bus Size
Select (SIZE) pin HIGH. The semaphore may be accessed through
the left port with CE
pins HIGH. A
are used in the same manner as a normal memory access. When
writing or reading a semaphore, the other address pins have no ef-
fect.
When writing to the semaphore, only I/O
written to the left port of an available semaphore, a 1 will appear at the
same semaphore address on the right port. That semaphore can
now only be modified by the port showing 0 (the left port in this case).
If the left port now relinquishes control by writing a 1 to the sema-
phore, the semaphore will be set to 1 for both ports. However, if the
right port had requested the semaphore (written a 0) while the left port
had control, the right port would immediately own the semaphore as
soon as the left port released it. Table 3 shows sample semaphore
operations.
BLC
after CE is taken LOW.
SWRD
+ t
BLC
0–2
DOE
PS
or t
represents the semaphore address. OE and R/W
of each other, the busy logic will determine which
PS
after the rising edge of the semaphore write. If the
0L
BLA
/CE
is violated, one port will definitely gain permis-
), otherwise, the slave chip may begin a write
[3]
1L
must remain HIGH during SEM LOW. A
[3]
active by asserting all B
are asserted and an address match
BLA
after an address match or
0R
/CE
0
CY7C056V
CY7C057V
is used. If a zero is
1R
active by assert-
0–3
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SOP
Byte Select
before at-