CYD09S18V18-200BBXC Cypress Semiconductor Corp, CYD09S18V18-200BBXC Datasheet - Page 50

• Manufacturer Part Number: CYD09S18V18-200BBXC
• Description: IC SRAM 9MBIT 200MHZ 256LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYD09S18V18-200BBXC

• Memory Size: 9M (512K x 18)
• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 1.42 V ~ 1.58 V, 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-LFBGA
• Memory Configuration: 512K X 18
• Clock Frequency: 77MHz
• Access Time: 3.3ns
• Supply Voltage Range: 1.42V To 1.58V, 1.7V To 1.9V
• Memory Case Style: BGA
• No. Of Pins: 256
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-2034; CYD09S18V18-200BBXC

Document History Page
Document Number: 38-06082 Rev. *J
Document Title: FullFlex™ Synchronous SDR Dual Port SRAM
Document Number: 38-06082
REV.
*G
*C
*D
*E
*F
ECN NO. Submission
402238
458131
470031
500001
627539
SEE ECN
SEE ECN
SEE ECN
SEE ECN
SEE ECN
Date
Orig. of
Change
KGH
YDT
YDT
YDT
QSL
Updated AC Test Load and Waveforms
Included FullFlex36 SDR 484-Ball BGA Pinout (Top View)
Included FullFlex18 SDR 484-Ball BGA Pinout (Top View)
Included Timing Parameter t
Changed ordering information with Pb-free part numbers
Removed VC_SEL
Added IO and core voltage adders
Removed references to bin drop for LVTTL/2.5 V LVCMOS and 1.5 V core modes
Updated Cin and Cout
Updated ICC, ISB1, ISB2 and ISB3 tables
Updated busy address read back timing diagram
Added HTSL input waveform
Removed HSTL (AC) from DC tables
Added 484-ball 27 mmx27 mmx2.33 mm PBGA package
Changed VOL of 1.8 V LVCMOS to 0.45 V
Updated tRSF
VREF is DNU when HSTL is not used
Formatted pin description table
Changed VDDIO pins for 36M x 36 and 36M x 18 pinouts
Changed 36Mx72 JTAG IDCODE
DLL Change, added Clock Input Cycle to Cycle Jitter
Modified DLL description
Changed Input Capacitance Table
Changed tCCS number
Added note 31
change all NC to DNU
corrected switching waveform for (CQEN = High) from both Pipeline and Flow
through mode to only pipeline mode
Modified master reset description
Modified switching characteristics tables, extracted signals effected by the DLL
into one table and combine all other signals into one table
updated package name
Added footnote for tHD, tHAC and tSAC
changed note 26 description
Description of Change
CORDY
Page 50 of 52
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