CY7C1520V18-200BZC Cypress Semiconductor Corp, CY7C1520V18-200BZC Datasheet - Page 10
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CY7C1520V18-200BZC
Manufacturer Part Number
CY7C1520V18-200BZC
Description
IC SRAM 72MBIT 200MHZ 165TFBGA
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C1520V18-167BZXC.pdf
(31 pages)
Specifications of CY7C1520V18-200BZC
Format - Memory
RAM
Memory Type
SRAM - Synchronous, DDR II
Memory Size
72M (2M x 36)
Speed
200MHz
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 70°C
Package / Case
165-TFBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C1520V18-200BZC
Manufacturer:
CYPRESS
Quantity:
250
Company:
Part Number:
CY7C1520V18-200BZC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C1520V18-200BZCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Truth Table
The truth table for the CY7C1516V18, CY7C1527V18, CY7C1518V18, and CY7C1520V18 follow.
Burst Address Table
(CY7C1518V18, CY7C1520V18)
Write Cycle Descriptions
The write cycle description table for CY7C1516V18 and CY7C1518V18 follows.
Notes
Document Number: 38-05563 Rev. *E
Write Cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
Read Cycle:
Load address; wait one and a half cycle;
read data on consecutive C and C rising edges.
NOP: No Operation
Standby: Clock Stopped
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device powers up deselected with the outputs in a tri-state condition.
4. On CY7C1518V18 and CY7C1520V18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses
5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
8. Is based on a write cycle that was initiated in accordance with the
BWS
NWS
H
H
H
H
sequence in the burst. On CY7C1516V18 and CY7C1527V18, “A1” represents A + ‘0’ and “A2” represents A + ‘1’.
symmetrically.
different portions of a write cycle, as long as the setup and hold requirements are achieved.
L
L
L
L
0
0
/
BWS
NWS
H
H
H
H
L
L
L
L
1
1
/
L–H
L–H
L–H
L–H
First Address (External)
K
–
–
–
–
Operation
L–H During the data portion of a write sequence:
L–H During the data portion of a write sequence:
L–H No data is written into the devices during this portion of a write operation.
L-H During the data portion of a write sequence:
K
–
–
–
–
X..X0
X..X1
During the data portion of a write sequence:
CY7C1516V18 − both nibbles (D
CY7C1518V18 − both bytes (D
CY7C1516V18 − both nibbles (D
CY7C1518V18 − both bytes (D
During the data portion of a write sequence:
CY7C1516V18 − only the lower nibble (D
CY7C1518V18 − only the lower byte (D
CY7C1516V18 − only the lower nibble (D
CY7C1518V18 − only the lower byte (D
During the data portion of a write sequence:
CY7C1516V18 − only the upper nibble (D
CY7C1518V18 − only the upper byte (D
CY7C1516V18 − only the upper nibble (D
CY7C1518V18 − only the upper byte (D
No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions
Stopped
L-H
L-H
L-H
K
[17:0]
[17:0]
[7:0]
[7:0]
) are written into the device.
) are written into the device.
) are written into the device.
) are written into the device.
[8:0]
[8:0]
[17:9]
[17:9]
LD
[3:0]
[3:0]
[7:4]
[7:4]
H
L
L
X
) is written into the device, D
) is written into the device, D
table. NWS
Comments
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
) is written into the device, D
[2, 8]
CY7C1516V18, CY7C1527V18
CY7C1518V18, CY7C1520V18
R/W
0
H
, NWS
L
X
X
Second Address (Internal)
1
, BWS
D(A1) at K(t + 1) ↑ D(A2) at K(t + 1) ↑
Q(A1) at C(t + 1)↑ Q(A2) at C(t + 2) ↑
High-Z
Previous State
0
X..X1
X..X0
, BWS
[2, 3, 4, 5, 6, 7]
DQ
1
, BWS
[17:9]
[17:9]
[8:0]
[8:0]
[7:4]
[7:4]
[3:0]
[3:0]
2
, and BWS
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
High-Z
Previous State
3
can be altered on
Page 10 of 31
DQ
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