CY7C1518AV18-250BZI Cypress Semiconductor Corp, CY7C1518AV18-250BZI Datasheet - Page 9

• Manufacturer Part Number: CY7C1518AV18-250BZI
• Description: IC SRAM 72MBIT 250MHZ 165TFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1518AV18-250BZI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 72M (4M x 18)
• Speed: 250MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-TFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Truth Table
The following is the truth table for parts, CY7C1518AV18 and CY7C1520AV18.
Burst Address Table
(CY7C1518AV18, CY7C1520AV18)
Write Cycle Descriptions
The following table represents the write cycle description for the part, CY7C1518AV18.
Notes
Document Number: 001-06982 Rev. *F
Write cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
Read cycle:
Load address; wait one and a half cycle;
read data on consecutive C and C rising edges.
NOP: No operation
Standby: Clock stopped
BWS
2. X = “Do not Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. On CY7C1518AV18 and CY7C1520AV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses
5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
8. Is based on a write cycle that was initiated in accordance with the
H
H
H
H
sequence in the burst.
symmetrically.
of a write cycle, as long as the setup and hold requirements are achieved.
L
L
L
L
00
BWS
H
H
H
H
L
L
L
L
1
L–H
L–H
L–H
L–H
First Address (External)
K
–
–
–
–
Operation
L–H During the data portion of a write sequence:
L–H During the data portion of a write sequence:
L–H No data is written into the devices during this portion of a write operation.
L-H During the data portion of a write sequence:
K
–
–
–
–
X..X0
X..X1
During the data portion of a write sequence:
Both bytes (D
Both bytes (D
During the data portion of a write sequence:
Only the lower byte (D
Only the lower byte (D
During the data portion of a write sequence:
Only the upper byte (D
Only the upper byte (D
No data is written into the devices during this portion of a write operation.
[17:0]
[17:0]
) are written into the device.
) are written into the device.
[8:0]
[8:0]
[17:9]
[17:9]
Write Cycle Descriptions
) is written into the device, D
) is written into the device, D
Stopped
) is written into the device, D
) is written into the device, D
L-H
L-H
L-H
K
LD
H
X
L
L
table. BWS
Comments
[2, 3, 4, 5, 6, 7]
0
R/W
, BWS
H
X
X
L
Second Address (Internal)
[17:9]
[17:9]
[8:0]
[8:0]
[2, 8]
1
, BWS
remains unaltered.
remains unaltered.
remains unaltered.
remains unaltered.
D(A1) at K(t + 1) ↑ D(A2) at K(t + 1) ↑
Q(A1) at C(t + 1)↑ Q(A2) at C(t + 2) ↑
High-Z
Previous state
2
, and BWS
X..X1
X..X0
DQ
3
can be altered on different portions
CY7C1518AV18
CY7C1520AV18
High-Z
Previous state
Page 9 of 28
DQ
[+] Feedback