CY7C1480BV33-200BZXI Cypress Semiconductor Corp, CY7C1480BV33-200BZXI Datasheet - Page 24

• Manufacturer Part Number: CY7C1480BV33-200BZXI
• Description: IC SRAM 72MBIT 200MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1480BV33-200BZXI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 72M (2M x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Characteristics
Over the Operating Range. Timing reference level is 1.5V when V
in (a) of
Document #: 001-15145 Rev. *A
Notes
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
14. This part has an internal voltage regulator; t
15. t
16. At any supplied voltage and temperature, t
17. This parameter is sampled and not 100% tested.
POWER
CYC
CH
CL
CO
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ADS
ADVS
WES
DS
CES
AH
ADH
ADVH
WEH
DH
CEH
be initiated.
from steady-state voltage.
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High-Z before Low-Z under the same system conditions.
CHZ
Parameter
, t
AC Test Loads and Waveforms
CLZ
,t
OELZ
, and t
V
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
Clock to High-Z
OE LOW to Output Valid
OE LOW to Output Low-Z
OE HIGH to Output High-Z
Address Setup Before CLK Rise
ADSC, ADSP Setup Before CLK Rise
ADV Setup Before CLK Rise
GW, BWE, BW
Data Input Setup Before CLK Rise
Chip Enable Setup Before CLK Rise
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
GW, BWE, BW
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
OEHZ
DD
(Typical) to the First Access
are specified with AC test conditions shown in part (b) of
[15, 16, 17]
X
X
OEHZ
[15, 16, 17]
POWER
Setup Before CLK Rise
Hold After CLK Rise
Description
on page 23 unless otherwise noted.
is less than t
is the time that the power needs to be supplied above V
[15, 16, 17]
[15, 16, 17]
OELZ
[14]
and t
CHZ
is less than t
DDQ
AC Test Loads and Waveforms
= 3.3V and is 1.25V when V
Min
CLZ
1.3
1.4
4.0
2.0
2.0
1.3
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
0
250 MHz
to eliminate bus contention between SRAMs when sharing the same data
CY7C1482BV33, CY7C1486BV33
Max
3.0
3.0
3.0
3.0
DD
(minimum) initially before a read or write operation can
Min
5.0
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
1
0
200 MHz
on page 23. Transition is measured ±200 mV
DDQ
Max
3.0
3.0
3.0
3.0
= 2.5V. Test conditions shown
CY7C1480BV33
Min
6.0
2.4
2.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
0
167 MHz
Max
3.4
3.4
3.4
3.4
Page 24 of 34
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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