IDT70T3539MS133BC IDT, Integrated Device Technology Inc, IDT70T3539MS133BC Datasheet - Page 4

• Manufacturer Part Number: IDT70T3539MS133BC
• Description: IC SRAM 18MBIT 133MHZ 256BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT70T3539MS133BC

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 2.4 V ~ 2.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 70T3539MS133BC; 800-1381

Pin Names
CE
R/W
OE
A
I/O
CLK
PL/FT
ADS
CNTEN
REPEAT
BE
IDT70T3539M
High-Speed 2.5V 512K x 36 Dual-Port Synchronous Static RAM
0L
0L
0L
0L
L
L
- A
L
,
L
Left Port
- I/O
- BE
CE
L
COL
V
18L
INT
OPT
L
ZZ
DDQL
L
1L
35L
3L
L
L
L
L
TRST
TMS
TDO
TCK
V
V
TDI
DD
SS
R/W
I/O
CLK
PL/FT
CE
OE
A
ADS
CNTEN
REPEAT
BE
0R
0R
0R
0R
R
R
R
- A
Right Port
R
,
- I/O
R
- BE
CE
COL
V
INT
OPT
18R
R
DDQR
ZZ
R
1R
35R
3R
R
R
R
R
Chip Enables (Input)
Read/Write Enable (Input)
Output Enable (Input)
Data Input/Output
Clock (Input)
Pipeline/Flow-Through (Input)
Counter Enable (Input)
Counter Repeat
Byte Enables (9-bit bytes) (Input)
Power (I/O Bus) (3.3V or 2.5V)
Option for selecting V
Sleep Mode pin
Power (2.5V)
Ground (0V) (Input)
Reset (Initialize TAP Controller) (Input)
Interrupt Flag (Output)
Collision Alert (Output)
Address (Input)
Address Strobe Enable (Input)
Test Data Input
Test Data Output
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
(1)
(Input)
(3)
Names
(4)
(Input)
(5)
DDQX
(1,2)
(Input)
(1)
5678 tbl 01
(5)
(Input)
6.42
4
NOTES:
1. V
2. OPT
3. When REPEAT
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
5. Chip Enables and Byte Enables are double buffered when PL/FT = V
applying inputs on the I/Os and controls for that port.
If OPT
levels and V
port's I/Os and address controls will operate at 2.5V levels and V
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
via ADS
asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode. It is recommended that
boundry scan not be operated during sleep mode.
signals take two cycles to deselect.
DD
, OPT
X
selects the operating voltage levels for the I/Os and controls on that port.
X
is set to V
X
.
X
, and V
DDQX
X
Industrial and Commercial Temperature Ranges
is asserted, the counter will reset to the last valid address loaded
DD
must be supplied at 3.3V. If OPT
DDQX
(2.5V), then that port's I/Os and controls will operate at 3.3V
must be set to appropriate operating levels prior to
X
is set to V
SS
(0V), then that
DDQX
IH
, i.e., the
must be