MAX6316MUK47BX-T Maxim Integrated, MAX6316MUK47BX-T Datasheet - Page 9
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MAX6316MUK47BX-T
Manufacturer Part Number
MAX6316MUK47BX-T
Description
Supervisory Circuits
Manufacturer
Maxim Integrated
Series
MAX6316, MAX6316M, MAX6317, MAX6318, MAX6319, MAX6320, MAX6321, MAX6322r
Datasheet
1.MAX1284ACSAT.pdf
(14 pages)
Specifications of MAX6316MUK47BX-T
Number Of Voltages Monitored
1
Monitored Voltage
1 V to 5.5 V
Undervoltage Threshold
4.63 V
Overvoltage Threshold
4.771 V
Output Type
Active Low, Bidirectional
Manual Reset
Resettable
Watchdog
Watchdog
Battery Backup Switching
No Backup
Power-up Reset Delay (typ)
28 ms
Supply Voltage - Max
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
SOT-23
Chip Enable Signals
No
Maximum Power Dissipation
571 mW
Minimum Operating Temperature
- 40 C
Power Fail Detection
No
Supply Current (typ)
10 uA
Supply Voltage - Min
1 V
P-channel transistor on-resistance quickly charges
stray capacitance on the reset line, allowing RESET to
transition from low to high within the required two elec-
tronic-clock cycles, even with several devices on the
reset line. This process occurs regardless of whether
the reset was caused by V
threshold, the watchdog timing out, MR being asserted,
or the µP or other device asserting RESET. The parts do
not require an external pullup. To minimize supply cur-
rent consumption, the internal 4.7kΩ pullup resistor dis-
connects from the supply whenever the MAX6316M/
MAX6318MH/MAX6319MH assert reset.
The MAX6320P/MAX6321HP/MAX6322HP have an
active-low, open-drain reset output. This output struc-
ture will sink current when RESET is asserted. Connect
a pullup resistor from RESET to any supply voltage up
to 6V (Figure 6). Select a resistor value large enough to
Figure 5. Bidirectional RESET Timing Diagram
Figure 6. MAX6320P/MAX6321HP/MAX6322HP Open-Drain
RESET Output Allows Use with Multiple Supplies
Maxim Integrated
RESET
V
CC
MR*
WDI**
RESET***
MAX6320
MAX6321
MAX6322
0.7V
+3.3V
RESET PULLED LOW
RESET GENERATOR
V
CC
BY µC OR
t
S
Open-Drain R R E E S S E E T T Output
RESET
µC RESET DELAY
GND
CC
t
OR
RP
10kΩ
dipping below the reset
5-Pin µP Supervisory Circuits with
***
**
TURNS ON
*
PULLUP
ACTIVE
MAX6320/MAX6322
MAX6320/MAX6321
MAX6321/MAX6322
5V SYSTEM
t
R
+5.0V
0.8 x V
Watchdog and Manual Reset
CC
register a logic low (see Electrical Characteristics ), and
small enough to register a logic high while supplying all
input current and leakage paths connected to the RESET
line. A 10kΩ pullup is sufficient in most applications.
The MAX6316_/MAX6317H/MAX6319_H/MAX6320P/
MAX6322HP feature a manual reset input. A logic low on
MR asserts a reset. After MR transitions low to high, reset
remains asserted for the duration of the reset timeout peri-
od (t
internal 52kΩ pullup resistor and therefore can be left
unconnected when not in use. MR can be driven with
TTL-logic levels in 5V systems, with CMOS-logic levels in
3V systems, or with open-drain or open-collector output
devices. A normally-open momentary switch from MR to
ground can also be used; it requires no external
debouncing circuitry. MR is designed to reject fast,
negative-going transients (typically 100ns pulses). A
0.1µF capacitor from MR to ground provides additional
noise immunity.
The MR input pin is equipped with internal ESD-protection
circuitry that may become forward biased. Should MR be
driven by voltages higher than V
would be drawn, which would damage the part. For
example, assume that MR is driven by a +5V supply other
than V
maximum rating is violated [-0.3V to (V
undesirable current flows through the ESD structure from
MR to V
the supply monitored by V
voltage at MR will never exceed V
The MAX6316_/MAX6317H/MAX6318_H/MAX6320P/
MAX6321HP feature a watchdog circuit that monitors
the µP’s activity. If the µP does not toggle the watchdog
input (WDI) within the watchdog timeout period (t
reset asserts. The internal watchdog timer is cleared by
reset or by a transition at WDI (which can detect pulses
as short as 50ns). The watchdog timer remains cleared
while reset is asserted. Once reset is released, the
timer begins counting again (Figure 7).
The WDI input is designed for a three-stated output
device with a 10µA maximum leakage current and the
capability of driving a maximum capacitive load of 200pF.
The three-state device must be able to source and sink at
least 200µA when active. Disable the watchdog function
by leaving WDI unconnected or by three-stating the driver
connected to WDI. When the watchdog timer is left open
circuited, the timer is cleared internally at intervals equal
to 7/8 of the watchdog period.
RP
CC
MAX6316–MAX6322
). The MR input is connected to V
CC
. If V
. To avoid this, use the same supply for MR as
CC
drops lower than +4.7V, MR’s absolute
CC
. This guarantees that the
Manual-Reset Input
CC
CC
.
Watchdog Input
, excessive current
CC
CC
+ 0.3V)], and
through an
WD
),
9