MAX795SCPA Maxim Integrated, MAX795SCPA Datasheet - Page 11

• Manufacturer Part Number: MAX795SCPA
• Description: Supervisory Circuits
• Manufacturer: Maxim Integrated
• Series: MAX793, MAX793R, MAX793S, MAX793T, MAX794, MAX795, MAX795R, MAX795S, MAX795Tr

Specifications of MAX795SCPA

• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V
• Undervoltage Threshold: Adjustable
• Overvoltage Threshold: Adjustable
• Output Type: Active Low, Open Drain
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: Backup
• Power-up Reset Delay (typ): 280 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Package / Case: PDIP N
• Chip Enable Signals: No
• Maximum Power Dissipation: 727 mW
• Minimum Operating Temperature: 0 C
• Power Fail Detection: No
• Supply Current (typ): 49 uA
• Supply Voltage - Min: 1 V

Figure 5. Watchdog Timing Relationship
a reset occurs or when a transition (low-to-high or high-
to-low) takes place at WDI. As long as reset is assert-
ed, the timer remains cleared and does not count. As
soon as reset is released or WDI changes state, the
timer starts counting (Figure 5). WDI can detect pulses
as short as 100ns. Unlike the 5V MAX690 family, the
watchdog function cannot be disabled.
In the MAX793/MAX794, WDO remains high (WDO is
pulled up to V
during the watchdog timeout period. WDO goes low if
no transition occurs at WDI during the watchdog timeout
period. The watchdog function is disabled and WDO is
a logic high when reset is asserted if V
WDO is a logic low when V
If a system reset is desired on every watchdog fault,
simply diode-OR connect WDO to MR (Figure 6).
When a watchdog fault occurs in this mode, WDO goes
low, pulling MR low, which causes a reset pulse to be
issued. Ten microseconds after reset is asserted, the
watchdog timer clears and WDO returns high. This
delay results in a 10µs pulse at WDO, allowing external
circuitry to capture a watchdog fault indication. A con-
tinuous high or low on WDI causes 200ms reset pulses
to be issued every 1.6s.
WDO CONNECTED TO µP INTERRUPT
RESET PULLED UP TO V
V
RESET
WDO
WDI
CC
Watchdog Output (MAX793/MAX794)
V
RST
CC
CC
) if there is a transition or pulse at WDI
______________________________________________________________________________________
t
RP
3.0V/3.3V Adjustable Microprocessor
CC
t
WD
is below V
CC
SW
is above V
.
SW
.
Internal gating of chip-enable (CE) signals prevents erro-
neous data from corrupting CMOS RAM in the event of an
undervoltage condition. The MAX793/MAX794/MAX795
use a series transmission gate from CE IN to CE OUT
During normal operation (reset not asserted), the CE
transmission gate is enabled and passes all CE transi-
tions. When reset is asserted, this path becomes dis-
abled, preventing erroneous data from corrupting the
CMOS RAM. The short CE propagation delay from CE IN
to CE OUT enables these µP supervisors to be used with
most µPs. If CE IN is low when reset asserts, CE OUT
remains low for typically 10µs to permit completion of the
current write cycle.
The CE transmission gate is disabled and CE IN is high
impedance (disabled mode) while reset is asserted.
During a power-down sequence when V
reset threshold, the CE transmission gate disables and
CE IN immediately becomes high impedance if the volt-
age at CE IN is high. If CE IN is low when reset asserts,
the CE transmission gate disables at the moment CE IN
goes high, or 10µs after reset asserts, whichever
occurs first (Figure 8). This permits the current write
cycle to complete during power-down.
Figure 6. Generating a Reset on Each Watchdog Fault
V
RESET
WDI
WDO
CC
Supervisory Circuits
t
RP
WDO
MR
MAX793/MAX794
t
Chip-Enable Signal Gating
WP
V
CC
RESET
t
RP
∼
10µs
Chip-Enable Input
CC
4.7kΩ
passes the
TO µP
11