MAX6735AKAZID4+T Maxim Integrated, MAX6735AKAZID4+T Datasheet - Page 10

• Manufacturer Part Number: MAX6735AKAZID4+T
• Description: Supervisory Circuits Single-/Dual-/Triple-Voltage N
• Manufacturer: Maxim Integrated
• Series: MAX6730A, MAX6731A, MAX6732A, MAX6733A, MAX6734A, MAX6735Ar

Specifications of MAX6735AKAZID4+T

• Number Of Voltages Monitored: 3
• Monitored Voltage: 0.9 V to 5 V
• Undervoltage Threshold: 4.5 V, 3 V
• Manual Reset: Resettable
• Watchdog: Watchdog
• Supply Voltage - Max: 5.5 V
• Maximum Power Dissipation: 714 mW
• Supply Current (typ): 15 uA
• Supply Voltage - Min: 0.8 V

The RSTIN comparator derives power from V
the input voltage must remain less than or equal to
V
large-valued resistors, resulting in reduced power con-
sumption of the system.
The watchdog feature monitors µP activity through
the watchdog input (WDI). A rising or falling edge on
WDI within the watchdog timeout period (t
cates normal µP operation. WDO asserts low if WDI
remains high or low for longer than the watchdog
timeout period. Floating WDI does not disable the
watchdog timer.
The MAX6730A–MAX6735A include a dual-mode
watchdog timer to monitor µP activity. The flexible time-
out architecture provides a long-period initial watchdog
mode, allowing complicated systems to complete
lengthy boots, and a short-period normal watchdog
mode, allowing the supervisor to provide quick alerts
when processor activity fails. After each reset event
(V
long initial watchdog period of 35s (min). The long
watchdog period mode provides an extended time for
the system to power up and fully initialize all µP and
system components before assuming responsibility for
routine watchdog updates.
Single-/Dual-/Triple-Voltage µP Supervisory
Circuits with Independent Watchdog Output
Figure 3. Watchdog Input/Output Timing Diagram ( MR and WDO Not Connected)
10
CC
CC
RSTIN
V
V
WDO
CC
WDI
RST
CC
1. Low leakage current at RSTIN allows the use of
1,
______________________________________________________________________________________
2
power-up, brownout, or manual reset), there is a
(MIN)
V
CC
V
TH
t
RP
<t
WD-L
Watchdog
WD
CC
1, and
) indi-
<t
WD-S
The usual watchdog timeout period (1.12s min) begins
after the initial watchdog timeout period (t
or after the first transition on WDI (Figure 3). During nor-
mal operating mode, the supervisor asserts the WDO
output if the µP does not update the WDI with a valid
transition (high to low or low to high) within the standard
timeout period (t
Connect MR to WDO to force a system reset in the
event that no rising or falling edge is detected at WDI
within the watchdog timeout period. WDO asserts low
when no edge is detected by WDI, the RST output
asserts low, the watchdog counter immediately clears,
and WDO returns high. The watchdog counter restarts,
using the long watchdog period, when the reset timeout
period ends (Figure 4).
The MAX6730A–MAX6735A guarantee proper opera-
tion down to V
valid reset levels down to V
down resistor from RST to GND. The resistor value
used is not critical, but it must be large enough not to
load the reset output when V
threshold. For most applications, 100kΩ is adequate.
Note that this configuration does not work for the open-
drain outputs of MAX6730A/MAX6732A/MAX6734A.
<t
WD-S
CC
WD-S
t
WD-S
= +0.8V. In applications that require
>t
WD-S
) (1.12s min).
Output Down to V
Ensuring a Valid Reset
CC
= 0V, use a 100kΩ pull-
CC
<t
is above the reset
WD-S
WD-L
<t
WD-S
CC
) expires
= 0V