CAT24C256LI-G ON Semiconductor, CAT24C256LI-G Datasheet - Page 6

• Manufacturer Part Number: CAT24C256LI-G
• Description: IC EEPROM 256KBIT 400KHZ 8DIP
• Manufacturer: ON Semiconductor

Specifications of CAT24C256LI-G

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 256K (32K x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Organization: 32 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.1 MHz
• Access Time: 3500 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 1 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Density: 256Kb
• Access Time (max): 500ns
• Frequency (max): 1MHz
• Write Protection: Yes
• Data Retention: 100Year
• Operating Supply Voltage (typ): 1.8/2.5/3.3/5V
• Package Type: PDIP
• Operating Temp Range: -40C to 85C
• Supply Current: 3mA
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 24C256LI-G

WRITE OPERATIONS
Byte Write
In Byte Write mode the Master sends a START, followed
by Slave address, two byte address and data to be
written (Figure 5). The Slave acknowledges all 4 bytes,
and the Master then follows up with a STOP, which in
turn starts the internal Write operation (Figure 6). During
internal Write, the Slave will not acknowledge any Read
or Write request from the Master.
Page Write
The CAT24C256 contains 32,768 bytes of data, arranged
in 512 pages of 64 bytes each. A two byte address word,
following the Slave address, points to the fi rst byte to be
written. The most signifi cant bit of the address word is
‘don’t care’, the next 9 bits identify the page and the last
6 bits identify the byte within the page. Up to 64 bytes
can be written in one Write cycle (Figure 7).
The internal byte address counter is automatically in-
cremented after each data byte is loaded. If the Master
transmits more than 64 data bytes, then earlier bytes will
be overwritten by later bytes in a ‘wrap-around’ fashion
(within the selected page). The internal Write cycle starts
immediately following the STOP.
Acknowledge Polling
Acknowledge polling can be used to determine if the
CAT24C256 is busy writing or is ready to accept com-
mands. Polling is implemented by interrogating the
device with a ‘Selective Read’ command (see READ
OPERATIONS).
The CAT24C256 will not acknowledge the Slave address,
as long as internal Write is in progress.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is pro-
tected against Write operations. If the WP pin is left fl oating
Doc. No. MD-1104, Rev. G
or is grounded, it has no impact on the operation of the
CAT24C256. The state of the WP pin is strobed on the
last falling edge of SCL immediately preceding the fi rst
data byte (Figure 8). If the WP pin is HIGH during the
strobe interval, the CAT24C256 will not acknowledge the
data byte and the Write request will be rejected.
Delivery State
The CAT24C256 is shipped erased, i.e., all bytes are
FFh.
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Characteristics subject to change without notice
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