HYB25D128800CE-6 Qimonda, HYB25D128800CE-6 Datasheet
HYB25D128800CE-6
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HYB25D128800CE-6 Summary of contents
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... All Qimonda update All Adapted internet edition Previous Revision: 2006-02, Rev. 1.5 5 Removed product type HYB25D128800CTL-6 and HYB25D128800CE-6 11 Added product type HYB25D128800CE-5, HYB25D128800CC-5 and HYB25D128800CC-6 74 Changed for D11 tRFC(DDR400) from programmed in byte 42 SPD Code Previous Revision: 2005-11, Rev. 1.4 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document ...
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Overview This chapter contains features and the description. 1.1 Features • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data used in capturing data at ...
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... A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edge- aligned with data for Reads and center-aligned with data for Writes. ...
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... HYB25D128160CE–6 2.5-3-3 ×4 HYB25D128400CE–6 ×8 HYB25D128800CE–6 HYB25D128800CF–6 ×4 HYB25D128400CE–7 1) HYB: designator for memory components 25D: DDR SDRAMs at ×8 and ×16 C: Die revision C T/E/C: Package type TSOP and FBGA L: Low power version (available on request) - these components are ...
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Pin Configuration The pin configuration of a DDR SDRAM is listed by function in column are explained in Table 5 and Table 6 TSOP package in Figure 2. Ball#/Pin# Name Pin Type Clock Signals G2 G3, ...
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Ball#/Pin# Name Pin Type Data Signals ×4 organization B7, 5 DQ0 I/O D7, 11 DQ1 I/O D3, 56 DQ2 I/O B3, 62 DQ3 I/O Data Strobe ×4 organisation E3, 51 DQS I/O Data Mask ×4 organization F3 ...
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Ball#/Pin# Name Pin Type Data Strobe ×16 organization E3, 51 UDQS I/O E7, 16 LDQS I/O Data Mask ×16 organization F3, 47 UDM I F7, 20 LDM I Power Supplies V F1 REF V A9, B2, C8, D2, ...
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Ball#/Pin# Name Pin Type F9, 14, 17, 19 25,43, 50, 53 Abbreviation Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I/O is ...
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Rev. 1.51, 2006-09 03292006-U5AN-6TI1 HYB25D128xxxC[C/E/F/T](L) 128-Mbit Double-Data-Rate SDRAM Pin Configuration P-TFBGA-60 Top View 10 Internet Data Sheet FIGURE 1 ...
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Rev. 1.51, 2006-09 03292006-U5AN-6TI1 HYB25D128xxxC[C/E/F/T](L) 128-Mbit Double-Data-Rate SDRAM Pin Configuration P-TSOPII-66-1 11 Internet Data Sheet FIGURE 2 ...
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... Functional Description The 128-Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. The 128-Mbit Double-Data-Rate SDRAM is internally configured as a quad-bank DRAM. The 128-Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double- data-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins ...
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Field Bits Type Description BL [2:0] w Burst Length Number of sequential bits per DQ related to one read/write command. Note: All other bit combinations are RESERVED. 001 2 B 010 4 B 011 ...
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Burst Length Starting Column Address ...
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BA1 BA0 A11 A10 0 1 reg. addr 1) Field Bits Type Description DLL 0 w DLL Status Drive Strength MODE [11:2] w Operating Mode Note: All other bit ...
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Name (Function) Write Enable Write Inhibit 1) Used to mask write data; provided coincident with the corresponding data. Current State CKE n-1 CKEn Previous Current Cycle Cycle Self Refresh L L Self Refresh L H Power Down L L Power ...
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Current State CS RAS CAS WE Any Idle Row Active ...
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Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank. 11) Requires appropriate DM masking. Truth Table 4: Current State Bank n - Command to Bank m (different bank) Current State CS RAS CAS WE Any ...
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Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8) Requires appropriate DM masking. 9) Concurrent Auto Precharge: This device supports “Concurrent Auto Precharge”. ...
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Electrical Characteristics This chapter lists the electrical characteristics. 4.1 Operating Conditions This chapter contains the operating conditions tables. Parameter V Voltage on I/O pins relative Voltage on inputs relative Voltage on supply ...
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Parameter Input Capacitance: CK, CK Delta Input Capacitance Input Capacitance: All other input-only pins Delta Input Capacitance: All other input-only pins Input/Output Capacitance: DQ, DQS, DM Delta Input/Output Capacitance: DQ, DQS These values are not subject to production ...
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Parameter Symbol V Device Supply Voltage DD V Device Supply Voltage DD V Output Supply Voltage DDQ V Output Supply Voltage DDQ V Supply Voltage, I/O Supply , SS V Voltage SSQ V Input Reference Voltage REF V Input Reference ...
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AC Characteristics (Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, Specifications and Conditions, and Electrical Characteristics and AC Timing.) Notes V 1. All voltages referenced Tests ...
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Parameter Input High (Logic 1) Voltage, DQ, DQS and DM Signals Input Low (Logic 0) Voltage, DQ, DQS and DM Signals Input Differential Voltage, CK and CK Inputs Input Closing Point Voltage, CK and CK Inputs V = 2.5 V ...
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DDR400B DDR333 Symbol Typ. Max. Typ DD0 100 70 DD1 95 110 3.5 DD2P DD2F DD2Q I ...
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Parameter DQ output access time from CK/CK CK high-level width Clock cycle time CK low-level width Auto precharge write recovery + precharge time DQ and DM input hold time DQ and DM input pulse width (each input) DQS output access ...
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Parameter Data-out low-impedance time from CK/CK Mode register set command cycle time DQ/DQS output hold time Data hold skew factor Active to Autoprecharge delay Active to Precharge command Active to Active/Auto-refresh command period Active to Read or Write delay Average ...
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The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the ...
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Parameter Data hold skew factor Active to Autoprecharge delay Active to Precharge command Active to Active/Auto-refresh command period Active to Read or Write delay Average Periodic Refresh Interval Auto-refresh to Active/Auto-refresh command period Precharge command period Read preamble Read postamble ...
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Package Outlines There are two package types used for this product family each in lead-free and lead-containing assembly: • P-TFBGA: Plastic Thin Fine-Pitch Ball Grid Array Package Description Ball Size Recommended Landing Pad Recommended Solder Mask Rev. 1.51, 2006-09 ...
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P-TSOPII: Plastic Thin Small Outline Package Type II Rev. 1.51, 2006-09 03292006-U5AN-6TI1 HYB25D128xxxC[C/E/F/T](L) 128-Mbit Double-Data-Rate SDRAM P(G)-TSOPII-66 (Plastic Thin Small Outline Package Type II) 31 Internet Data Sheet FIGURE 5 ...
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List of Figures Figure 1 Pin Configuration P-TFBGA-60 Top View ...
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List of Tables Table 1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system ...