AT24C32C-PU Atmel, AT24C32C-PU Datasheet

IC EEPROM 32KBIT 1MHZ 8DIP

AT24C32C-PU

Manufacturer Part Number
AT24C32C-PU
Description
IC EEPROM 32KBIT 1MHZ 8DIP
Manufacturer
Atmel
Datasheet

Specifications of AT24C32C-PU

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
32K (4K x 8)
Speed
400kHz, 1MHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Organization
4 K x 8
Interface Type
2-Wire
Maximum Clock Frequency
1 MHz
Access Time
550 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.8 V
Maximum Operating Current
3 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
1.8 V, 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT24C32C-PU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
(Features
Description
The AT24C32C/64C provides 32,768/65,536 bits of serial electrically erasable and
programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits
each. The device’s cascadable feature allows up to 8 devices to share a common 2-
wire bus. The device is optimized for use in many industrial and commercial applica-
tions where low power and low voltage operation are essential. The AT24C32C/64C is
available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Lead Frame
Land Grid Array (ULA), 8-lead TSSOP, 8-lead Ultra Thin Mini-MAP (MLP2x3) and, 8-
ball dBGA2 packages and is accessed via a 2-wire serial interface. In addition, the
entire family is available in 1.8V (1.8 to 5.5V) version.
Pin Configurations
Pin Name
A0 - A2
SDA
SCL
WP
Low-voltage and Standard-voltage Operation
Internally Organized 4096 x 8, 8192 x 8
2-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
1 MHz (5.0V) and 400 KHz (1.8V Compatibility)
Write Protect Pin for Hardware Data Protection
32-Byte Page Write Mode (Partial Page Writes Allowed)
Self-Timed Write Cycle (5 ms max)
High Reliability
Lead-free/Halogen-free Devices
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead
TSSOP, 8-lead Ultra Thin Mini-MAP (MLP2x3), and 8-ball dBGA2 Packages.
Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
– 1.8 (V
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
CC
= 1.8 to 5.5V)
Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
GND
A0
A1
A2
Mini-MAP (MLP 2x3)
VCC
SDA
SCL
VCC
SDA
SCL
WP
WP
8-lead Ultra Thin
8-ball dBGA2
8-lead SOIC
Bottom View
Bottom View
1
2
3
4
8
7
6
5
8
7
6
5
1
2
3
4
1
2
3
4
8
7
6
5
A0
A1
A2
GND
A0
A1
A2
GND
VCC
WP
SCL
SDA
GND
8-lead Ultra Lead Frame
GND
Land Grid Array (ULA)
A0
A1
A2
VCC
SDA
SCL
A0
A1
A2
WP
8-lead TSSOP
Bottom View
8
7
6
5
8-lead PDIP
1
2
3
4
1
2
3
4
1
2
3
4
8
7
6
5
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
VCC
WP
SCL
SDA
2-Wire
Serial EEPROM
32K (4096 x 8)
64K (8192 x 8)
AT24C32C
AT24C64C
Not Recommended
for New Design
5298A–SEEPR–1/08

Related parts for AT24C32C-PU

AT24C32C-PU Summary of contents

Page 1

... The device’s cascadable feature allows devices to share a common 2- wire bus. The device is optimized for use in many industrial and commercial applica- tions where low power and low voltage operation are essential. The AT24C32C/64C is available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead TSSOP, 8-lead Ultra Thin Mini-MAP (MLP2x3) and, 8- ball dBGA2 packages and is accessed via a 2-wire serial interface ...

Page 2

... Storage Temperature......................................... -65 to +150°C Voltage on Any Pin with Respect to Ground ....................................... -1.0 to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5 Block Diagram VCC GND WP SCL SDA AT24C32C/64C 2 *NOTICE: START STOP LOGIC SERIAL CONTROL LOGIC LOAD COMP DEVICE ADDRESS LOAD COMPARATOR R/W DATA WORD ADDR/COUNTER ...

Page 3

... If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive cou- pling to the circuit board V the pin to GND. 5298A–SEEPR–1/08 plane is <3pF. If coupling is >3pF, Atmel CC , all write operations to the memory are inhibited. CC plane is <3pF. If coupling is >3pF, Atmel recommends connecting CC AT24C32C/64C ® recommends 3 ...

Page 4

... Memory Organization AT24C32C/64C, 32/64K SERIAL EEPROM: The 32K/64K is internally organized as 128/256 pages of 32 bytes each. Random word addressing requires a 12/13 bit data word address. Pin Capacitance (1) Applicable over recommended operating range from T Symbol Test Condition C Input/Output Capacitance (SDA) I/O C Input Capacitance (A ...

Page 5

... Input and output timing reference voltages: 0.5 V 5298A–SEEPR–1/08 = -40°C to +85° 1.8-volt Min 1.3 0.6 (1) 0.05 1.3 (1) 0.6 0.6 0 100 0 0 AT24C32C/64C = +1.8V to +5.5V TTL Gate and CC 5.0-volt Max Min Max Units 400 1000 kHz 0.4 µs 0.4 µs 100 50 ns 0.9 0.05 0.55 µs 0.5 µ ...

Page 6

... EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl- edge that it has received each word. STANDBY MODE: The AT24C32C/64C features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the Stop bit and the completion of any internal operations ...

Page 7

... The write cycle time t is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. WR 5298A–SEEPR–1/08 t HIGH LOW LOW t t HD.STA HD.DAT t AA ACK t wr STOP CONDITION AT24C32C/64C SU.DAT t DH (1) START CONDITION SU.STO t BUF 7 ...

Page 8

... Data Validity SDA SCL 8. Start and Stop Definition SDA SCL 9. Output Acknowledge SCL DATA IN DATA OUT AT24C32C/64C 8 DATA STABLE DATA STABLE DATA CHANGE START 1 START STOP 8 9 ACKNOWLEDGE 5298A–SEEPR–1/08 ...

Page 9

... Upon a compare of the device address, the EEPROM will output a zero compare is not made, the device will return to standby state. DATA SECURITY: The AT24C32C/64C has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin 11. Write Operations BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment ...

Page 10

... The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 12-1. Device Address Figure 12-2. Byte Write AT24C32C/64C 10 Figure 12-5 on page 12). Figure 12-6 ...

Page 11

... Figure 12-3. Page Write Note DON’T CARE bits DON’T CARE bit for AT24C32C Figure 12-4. Current Address Read Figure 12-5. Random Read Note DON’T CARE bits 5298A–SEEPR–1/08 t AT24C32C/64C 11 ...

Page 12

... Figure 12-6. Sequential Read AT24C32C/64C 12 5298A–SEEPR–1/08 ...

Page 13

... AT24C32C Ordering Information Ordering Code AT24C32C-PU (Bulk form only) (1) AT24C32CN-SH-B (NiPdAu Lead Finish) (2) AT24C32CN-SH-T (NiPdAu Lead Finish) (1) AT24C32C-TH-B (NiPdAu Lead Finish) (2) AT24C32C-TH-T (NiPdAu Lead Finish) (2) AT24C32CY6-YH-T (NiPdAu Lead Finish) (2) AT24C32CD3-DH-T (NiPdAu Lead Finish) (2) AT24C32CU2-UU-T (3) AT24C32C-W-11 Notes: 1. “-B” denotes Bulk. 2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini-MAP and dBGA2 = 5K per reel. ...

Page 14

... Body, Plastic, Thin Shrink Small Outline Package (TSSOP) 8U2-1 8-ball, die Ball Grid Array Package (dBGA2) 8D3 8-lead, 1. 2.20 mm Body, Ultra Lead Frame Land Grid Array (ULA) -1.8 Low Voltage (1.8V to 5.5V) AT24C32C/64C 14 Voltage Package 1.8 8P3 1.8 8S1 1 ...

Page 15

... BOTTOM MARK Seal Year Y = SEAL YEAR | Seal Week 6: 2006 | | | 7: 2007 8: 2008 2009 Lot Number to Use ALL Characters in Marking BOTTOM MARK AT24C32C/64C WW = SEAL WEEK 0: 2010 02 = Week 2 1: 2011 04 = Week 4 2: 2012 :: : :::: : 3: 2013 :: : :::: :: 50 = Week Week 52 No Bottom Mark WW = SEAL WEEK 0: 2010 02 = Week 2 1: 2011 ...

Page 16

... Pin 1 Indicator 13.4 8-Ultra Thin Mini MAP TOP MARK |---|---|---| |---|---|---| H 1 |---|---|---| |---|---|---| * | Pin 1 Indicator (Dot) AT24C32C/64C SEAL YEAR 6: 2006 7: 2007 W 8: 2008 9: 2009 YEAR OF ASSEMBLY XX = ATMEL LOT NUMBER TO COORESPOND WITH NSEB TRACE CODE LOG BOOK. (e. AA, AB, AC,...AX, AY, AZ SEAL YEAR 6: 2006 7: 2007 8: 2008 ...

Page 17

... TOP MARK |---|---|---| |---|---|---| |---|---|---| * | Pin 1 Indicator (Dot) 5298A–SEEPR–1/08 AT24C32C/64C Y = YEAR OF ASSEMBLY XX = ATMEL LOT NUMBER TO COORESPOND WITH NSEB TRACE CODE LOG BOOK. (e. AA, AB, AC,...AX, AY, AZ BUILD YEAR 6: 2006 7: 2007 8: 2008 Etc... 17 ...

Page 18

... Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 14.2 8-SOIC TOP MARK |---|---|---|---|---|---|---|---| |---|---|---|---|---|---|---|---| |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) AT24C32C/64C SEAL YEAR Seal Week 6: 2006 | | 7: 2007 8: 2008 2009 Lot Number to Use ALL Characters in Marking BOTTOM MARK Seal Year Y = SEAL YEAR | Seal Week 6: 2006 | | | 7: 2007 8: 2008 Y ...

Page 19

... W 8: 2008 9: 2009 YEAR OF ASSEMBLY XX = ATMEL LOT NUMBER TO COORESPOND WITH NSEB TRACE CODE LOG BOOK. (e. AA, AB, AC,...AX, AY, AZ SEAL YEAR 6: 2006 7: 2007 8: 2008 9: 2009 AT24C32C/64C WW = SEAL WEEK 0: 2010 02 = Week 2 1: 2011 04 = Week 4 2: 2012 :: : :::: : 3: 2013 :: : :::: :: 50 = Week Week 52 0: 2010 1: 2011 2: 2012 ...

Page 20

... TOP MARK |---|---|---| |---|---|---| |---|---|---| * | Pin 1 Indicator (Dot) AT24C32C/64C YEAR OF ASSEMBLY XX = ATMEL LOT NUMBER TO COORESPOND WITH NSEB TRACE CODE LOG BOOK. (e. AA, AB, AC,...AX, AY, AZ BUILD YEAR 6: 2006 7: 2007 8: 2008 Etc... 5298A–SEEPR–1/08 ...

Page 21

... San Jose, CA 95131 R 5298A–SEEPR–1/08 Pin 1 Pin 1 Index Index Area Area TITLE 8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map, Dual No Lead Package (DFN) ,(MLP 2x3) AT24C32C/64C (6X) e (6X 1.50 REF. 1.50 REF. COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM D 2 ...

Page 22

... D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 2325 Orchard Parkway San Jose, CA 95131 R AT24C32C/64C ...

Page 23

... These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R 5298A–SEEPR–1/ TITLE 8S1, 8-lead (0.150 Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) AT24C32C/64C END VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A1 0.10 – 0.25 DRAWING NO. ...

Page 24

... Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and ad acent lead is 0.07 mm. 5. Dimension D and determined at Datum Plane H. 2325 Orchard Parkway San Jose, CA 95131 R AT24C32C/64C TITLE 8A2, 8-lead, 4 ...

Page 25

... D E TOP VIEW A1 BALL PAD CORNER (d1) BOTTOM VIEW 8 SOLDER BALLS TITLE 8U2-1, 8-ball, 2.35 x 3.73 mm Body, 0.75 mm pitch, Small Die Ball Grid Array Package (dBGA2) AT24C32C/64C SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 0.81 0.91 1.00 A 0.15 0.20 0.25 ...

Page 26

... ULA PIN # TOP VIEW 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT24C32C/64C SIDE VIEW SYMBOL TITLE 8D3, 8-lead (1.80 x 2.20 mm Body) Ultra Leadframe Land Grid Array (ULLGA PIN # BOTTOM VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE – – ...

Page 27

... Revision History Doc. Rev. 5298A 5298A–SEEPR–1/08 Date Comments AT24C32C/64C product with date code 2008 work week 14 (814) or later supports 5Vcc operation 1/2008 Initial document release AT24C32C/64C 27 ...

Page 28

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...

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