DS1815R-5-U+ Maxim Integrated, DS1815R-5-U+ Datasheet - Page 9

• Manufacturer Part Number: DS1815R-5-U+
• Description: Supervisory Circuits
• Manufacturer: Maxim Integrated
• Series: DS1815r

Specifications of DS1815R-5-U+

• Number Of Voltages Monitored: 1
• Monitored Voltage: 0 V to 5.5 V
• Undervoltage Threshold: 2.98 V
• Overvoltage Threshold: 3.15 V
• Output Type: Active Low, Push-Pull
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Power-up Reset Delay (typ): 250 ms
• Supply Voltage - Max: 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-23
• Chip Enable Signals: No
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: Yes
• Supply Current (typ): 35 uA
• Supply Voltage - Min: 0 V
• Part # Aliases: 90-1815R+U05

The watchdog’s circuit monitors the µP’s activity. It the
µP does not toggle the watchdog input (WDI) within
t
out period. The internal watchdog timer is cleared by
any event that asserts RESET, by a falling transition at
WDI (which can detect pulses as short as 300ns) or by
a transition at WDS. The watchdog timer remains
cleared while reset is asserted; as soon as reset is
released, the timer starts counting.
The MAX6746–MAX6751 feature two modes of watch-
dog operation: normal mode and extended mode. In nor-
mal mode (Figure 4a), the watchdog timeout period is
determined by the value of the capacitor connected
between SWT and ground. In extended mode (Figure
4b), the watchdog timeout period is multiplied by 128.
For example, in extended mode, a 0.1µF capacitor gives
a watchdog timeout period of 65s (see the Extended-
Mode Watchdog Timeout Period vs. C
Typical Operating Characteristics ). To disable the watch-
dog timer function, connect SWT to ground.
The MAX6752 and MAX6753 have a windowed watch-
dog timer that asserts RESET for the adjusted reset
timeout period when the watchdog recognizes a fast
watchdog fault (t
(period > t
independently of the watchdog timeout period.
The slow watchdog period, t
with t
The fast watchdog period, t
from the slow watchdog fault period (t
fast watchdog period by pinstrapping SET0 and SET1,
Figure 4b. Watchdog Timing Diagram, WDS = V
WD
(user-selected), RESET asserts for the reset time-
WD2
RESET
EXTENDED MODE (WDS = V
WDI
µP Reset Circuits with Capacitor-Adjustable
in seconds and C
V
V
OV
OV
WD2
CC
CC
t
). The reset timeout period is adjusted
WD2
WDI
_______________________________________________________________________________________
= 0.65 x 10
< t
CC
WD1
)
WD2
SWT
WD1
), or a slow watchdog fault
9
, is selectable as a ratio
in Farads.
is calculated as follows:
x C
MAX6746–MAX6751
Watchdog Timer
MAX6752/MAX6753
SWT
SWT
WD2
Reset/Watchdog Timeout Delay
CC
graph in the
). Select the
t
WD
x 128
Table 1. Min/Max Watchdog Setting
where HIGH is V
trates the SET0 and SET1 configuration for the 8, 16,
and 64 window ratio ( t
For example, if C
low, then t
RESET asserts if the watchdog input has two falling
edges too close to each other (faster than t
5a) or falling edges that are too far apart (slower than
t
played in (Figure 5c). The internal watchdog timer is
cleared when a WDI falling edge is detected within the
valid watchdog window or when RESET is deasserted.
All WDI inputs are ignored while RESET is asserted.
The watchdog timer begins to count after RESET is
deasserted. The watchdog timer clears and begins to
count after a valid WDI falling logic input. WDI falling
transitions within periods shorter than t
than t
out period. WDI falling transitions within the t
t
between t
t
RESET. To guarantee that the window watchdog does
not assert the RESET, strobe WDI between t
and t
RESET is asserted or after a falling transition on WDI or
after a state change on SET0 or SET1. Disable the
watchdog timer by connecting SET0 high and SET1 low.
WD2(max)
WD2
WD2
SET0
HIGH
HIGH
LOW
LOW
) (Figure 5b). Normal watchdog operation is dis-
WD2(min)
WD2
window do not assert RESET. WDI transitions
WD2
are not guaranteed to assert or deassert the
force RESET to assert low for the reset time-
WD1(min)
SET1
HIGH
HIGH
LOW
LOW
is 975ms (typ) and t
. The watchdog timer is cleared when
SWT
CC
and t
is 1500pF, and SET0 and SET1 are
and LOW is GND. Table 1 illus-
WD2
/t
WD1(max)
WD1
Watchdog Disabled
).
WD1
RATIO
16
64
or t
8
is 122ms (typ).
WD1
WD2(min)
WD1
or longer
WD1(max)
WD1
t
RP
) (Figure
and
and
9