25LC160/P Microchip Technology, 25LC160/P Datasheet - Page 13

• Manufacturer Part Number: 25LC160/P
• Description: IC EEPROM 16KBIT 2MHZ 8DIP
• Manufacturer: Microchip Technology

Specifications of 25LC160/P

• Memory Size: 16K (2K x 8)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 2MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Memory Configuration: 2K X 8 / 1K X 16
• Ic Interface Type: SPI
• Clock Frequency: 2MHz
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: DIP
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 25LC160/PR; 25LC160/PR

3.6
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the STATUS
register as shown in Table 3-2. The user is able to
select one of four levels of protection for the array by
writing to the appropriate bits in the STATUS register.
The array is divided up into four segments. The user
has the ability to write-protect none, one, two or all four
of the segments of the array. The partitioning is
controlled as shown in Table 3-3.
TABLE 3-3:
TABLE 3-4:
FIGURE 3-7:
© 2009 Microchip Technology Inc.
SCK
Note:
CS
SO
SI
Write Status Register Instruction
(WRSR)
Density
128K
256K
BP1
16K
32K
64K
An internal write cycle (T
sequence.
8K
0
0
1
1
0
0
ARRAY PROTECTION
ARRAY PROTECTED ADDRESS LOCATIONS
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
0
1
0
Instruction
2
1800h - 1FFFh
3000h - 3FFFh
6000h - 7FFFh
C00h - FFFh
0
300h - 3FFh
600h - 7FFh
3
Upper 1/4
WC
BP0
0
0
1
0
1
4
) is initiated on the rising edge of CS after a valid write STATUS register
0
5
High-Impedance
Preliminary
0
6
1
Array Addresses
7
Write-Protected
1000h - 1FFFh
2000h - 3FFFh
4000h - 7FFFh
800h - FFFh
200h - 3FFh
400h - 7FFh
Upper 1/2
Upper 1/4
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the
programmable hardware write-protect feature. Hard-
ware write protection is enabled when WP pin is low
and the WPEN bit is high. Hardware write protection is
disabled when either the WP pin is high or the WPEN
bit is low. When the chip is hardware write-protected,
only writes to nonvolatile bits in the STATUS register
are disabled. See Table 5-1 for a matrix of functionality
on the WPEN bit.
See Figure 3-7 for the WRSR timing sequence.
Upper 1/2
7
8
None
All
6
9
Data to STATUS Register
10
5
11
4
Array Addresses
12
3
0000h - 1FFFh
0000h - 3FFFh
0000h - 7FFFh
Unprotected
000h - 3FFh
000h - 7FFh
000h - FFFh
Lower 3/4
Lower 1/2
None
25LCXXX
13
2
All
All
14
1
DS22131C-page 13
15
0