25LC128-I/ST Microchip Technology, 25LC128-I/ST Datasheet - Page 11
![IC EEPROM 128KBIT 10MHZ 8TSSOP](/photos/6/59/65937/c04-086_st_sml.jpg)
25LC128-I/ST
Manufacturer Part Number
25LC128-I/ST
Description
IC EEPROM 128KBIT 10MHZ 8TSSOP
Manufacturer
Microchip Technology
Datasheet
1.25AA128-IP.pdf
(26 pages)
Specifications of 25LC128-I/ST
Memory Size
128K (16K x 8)
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
10MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-TSSOP
Memory Configuration
16K X 8
Ic Interface Type
SPI
Clock Frequency
10MHz
Supply Voltage Range
2.5V To 5.5V
Memory Case Style
TSSOP
No. Of Pins
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
25LC128-I/ST(25LC128-E/ST)
Manufacturer:
BX
Quantity:
2 500
2.6
The Write Status Register (WRSR) instruction allows the
user to write to the nonvolatile bits in the STATUS reg-
ister as shown in Table 2-2. The user is able to select
one of four levels of protection for the array by writing
to the appropriate bits in the STATUS register. The
array is divided up into four segments. The user has the
ability to write-protect none, one, two, or all four of the
segments of the array. The partitioning is controlled as
shown in Table 2-3.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the
programmable hardware write-protect feature. Hard-
ware write protection is enabled when WP pin is low
and the WPEN bit is high. Hardware write protection is
disabled when either the WP pin is high or the WPEN
bit is low. When the chip is hardware write-protected,
FIGURE 2-7:
© 2009 Microchip Technology Inc.
SCK
Note:
CS
SO
SI
Write Status Register (WRSR)
An internal write cycle (T
0
0
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
0
1
0
Instruction
2
0
3
WC
0
4
) is initiated on the rising edge of CS after a valid write STATUS register
0
5
High-Impedance
0
6
1
7
only writes to nonvolatile bits in the STATUS register
are disabled. See Table 2-4 for a matrix of functionality
on the WPEN bit.
See Figure 2-7 for the WRSR timing sequence.
TABLE 2-3:
7
8
BP1
0
0
1
1
6
25AA128/25LC128
9
Data to STATUS Register
10
5
11
4
ARRAY PROTECTION
BP0
0
1
0
1
12
3
13
2
Array Addresses
Write-Protected
(3000h-3FFFh)
(2000h-3FFFh)
(0000h-3FFFh)
14
upper 1/4
upper 1/2
1
DS21831D-page 11
none
all
15
0