IS61LPS51236A-200TQLI ISSI, Integrated Silicon Solution Inc, IS61LPS51236A-200TQLI Datasheet - Page 25

• Manufacturer Part Number: IS61LPS51236A-200TQLI
• Description: IC SRAM 18MBIT 200MHZ 100TQFP
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS61LPS51236A-200TQLI

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Density: 18Mb
• Access Time (max): 3.1ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 4
• Supply Current: 475mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1100; IS61LPS51236A-200TQLI

IS61VPS25672A, IS61LPS25672A
IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A
TAP Electrical Characteristics Over the Operating Range
Notes:
TAP AC ELECTRICAL CHARACTERISTICS
Notes:
1. Both t
2. Test conditions are specified using the load in TAP AC test conditions. t
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. N
02/12/2010
Symbol
V
V
V
V
V
V
I
1. All Voltage referenced to Ground.
2. Overshoot: V
X
Symbol Parameter
t
f
t
t
t
t
t
t
t
t
t
t
OH1
OH2
OL1
OL2
IH
IL
TCYC
TF
TH
TL
TMSS
TDIS
CS
TMSH
TDIH
CH
TDOV
TDOX
Undershoot: V
Power-up: V
CS
and t
TCK Clock cycle time
TCK Clock frequency
TCK Clock HIGH
TCK Clock LOW
TMS setup to TCK Clock Rise
TDI setup to TCK Clock Rise
Capture setup to TCK Rise
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture hold after Clock Rise
TCK LOW to TDO valid
TCK LOW to TDO invalid
CH
IH
IH
IL
< 2.6V and V
refer to the set-up and hold time requirements of latching data from the boundary scan register.
(AC) ≤ V
(AC)
Parameter
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
≤
0.5V for t
DD
+1.5V for t
DD
< 2.4V and V
≤
t
TCYC
≤
t
/2,
TCYC
DDQ
/2,
< 1.4V for t < 200 ms.
(1,2)
Test Conditions
V
(OVER OPERATING RANGE)
I
I
SS
OH
I
OH
I
OL
OL
≤ V I ≤ V
= –2.0 mA
= –100 µA
= 2.0 mA
= 100 µA
R
/t
F
(1,2)
= 1 ns.
DDQ
Min.
100
40
40
10
10
10
10
10
10
—
—
0
Max.
10
20
—
—
—
—
—
—
—
—
—
—
Min.
–0.3
–10
1.7
2.1
1.7
—
—
V
DD
Max.
MHz
0.7
0.2
0.7
Unit
10
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
+0.3
Units
µA
V
V
V
V
V
V
25