W9412G6JH-5 Winbond Electronics, W9412G6JH-5 Datasheet - Page 26

• Manufacturer Part Number: W9412G6JH-5
• Description: IC DDR-400 SDRAM 128MB 66TSSOPII
• Manufacturer: Winbond Electronics

Specifications of W9412G6JH-5

• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 128M (8Mx16)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 66-TSOPII
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.6
t
t
SYM.
t
t
WPRES
t
t
t
DQSCK
t
t
t
t
t
t
t
WPRE
t
t
t
DQSQ
DQSH
WPST
t
t
t
t
t
t
t
RPRE
RPST
DQSL
t
t
DQSS
XSNR
XSRD
DIPW
t
T(SS)
t
WTR
t
RCD
CCD
RRD
t
t
t
REFI
MRD
RFC
RAS
RAP
t
t
t
t
t
t
DSS
DSH
t
DAL
IPW
t
WR
t
t
t
t
RC
CH
QH
DH
RP
CK
AC
CL
HP
DS
HZ
LZ
IS
IH
IS
IH
AC Characteristics and Operating Condition
Active to Ref/Active Command Period
Ref to Ref/Active Command Period
Active to Precharge Command Period
Active to Read/Write Command Delay Time
Active to Read with Auto-precharge Enable
Read/Write(a) to Read/Write(b) Command Period
Precharge to Active Command Period
Active(a) to Active(b) Command Period
Write Recovery Time
Auto-precharge Write Recovery + Precharge Time
CLK Cycle Time
Data Access Time from CLK, CLK
DQS Output Access Time from CLK, CLK
Data Strobe Edge to Output Data Edge Skew
CLk High Level Width
CLK Low Level Width
CLK Half Period (minimum of actual t
DQ Output Data Hold Time from DQS
DQS Read Preamble Time
DQS Read Postamble Time
DQ and DM Setup Time to DQS, slew rate 0.5V/nS
DQ and DM Hold Time to DQS, slew rate 0.5V/nS
DQ and DM Input Pulse Width (for each input)
DQS Input High Pulse Width
DQS Input Low Pulse Width
DQS Falling Edge to CLK Setup Time
DQS Falling Edge Hold Time from CLK
Clock to DQS Write Preamble Set-up Time
DQS Write Preamble Time
DQS Write Postamble Time
Write Command to First DQS Latching Transition
Input Setup Time (fast slew rate)
Input Hold Time (fast slew rate)
Input Setup Time (slow slew rate)
Input Hold Time (slow slew rate)
Control & Address Input Pulse Width (for each input)
Data-out High-impedance Time from CLK, CLK
Data-out Low-impedance Time from CLK, CLK
SSTL Input Transition
Internal Write to Read Command Delay
Exit Self Refresh to non-Read Command
Exit Self Refresh to Read Command
Refresh Interval Time (4K/ 64mS)
Mode Register Set Cycle Time
PARAMETER
CH,
CL = 2
CL = 2.5
CL = 3
CL = 4
t
CL
)
- 26 -
(t
(t
(t
t
WR
HP
RP
-0.65
-0.55
CL
MIN.
0.45
0.45
1.75
0.35
0.35
0.25
0.85
-0.7
min
200
0.9
0.4
0.4
0.4
0.2
0.2
0.4
0.6
0.6
0.7
0.7
2.2
0.5
48
60
40
16
16
16
12
12
72
1
+
4
4
0
2
8
,t
-0.5
/t
-
-
/t
CH
CK
CK
)
)
)
-4
70000
MAX.
0.65
0.55
0.55
0.55
1.15
15.6
0.4
1.1
0.6
0.6
0.7
0.7
1.5
12
12
-
-
Publication Release Date: Apr. 02, 2010
(t
(t
(t
t
WR
HP
RP
CL
MIN.
0.45
0.45
Min,
1.75
0.35
0.35
0.25
0.75
-0.7
-0.6
-0.7
200
7.5
0.9
0.4
0.4
0.4
0.2
0.2
0.4
0.6
0.6
0.7
0.7
2.2
0.5
50
70
40
15
15
15
10
15
75
10
1
+
6
5
0
2
,t
-0.5
/t
-
/t
CH
CK
CK
)
)
)
-5
100000
MAX.
0.55
0.55
1.25
15.6
0.7
0.6
0.4
1.1
0.6
0.6
0.7
0.7
1.5
W9412G6JH
12
12
12
-
UNIT
t
t
t
t
t
t
t
t
nS
nS
nS
nS
nS
nS
nS
nS
µS
nS
CK
CK
CK
CK
CK
CK
CK
CK
Revision A01
19, 21-23
19, 21-23
NOTES
20-23
20-23
18
16
16
11
11
11
11
17