CY62148DV30LL-55SXI Cypress Semiconductor Corp, CY62148DV30LL-55SXI Datasheet

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... Note: 1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on Cypress Semiconductor Corporation Document #: 38-05341 Rev. *D 4-Mbit (512K x 8) MoBL Functional Description The CY62148DV30 is a high-performance CMOS static RAM organized as 512K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ ...

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... Range CY62148DV30L Industrial CY62148DV30LL Industrial CY62148DV30LL Industrial CY62148DV30LL Automotive-A Notes pins are not connected on the die. 3. DNU pins have to be left floating or tied to Vss to ensure proper application. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V Document #: 38-05341 Rev ...

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... Document #: 38-05341 Rev. *D Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range Product + 0.3V CC(max) CY62148DV30L CY62148DV30LL + 0.3V CC(max) CY62148DV30LL Automotive-A –40°C to +85°C + 0.3V CC(max) Test Conditions = 2.20V CC = 2.70V 2.20V 2.70V CC < ...

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Capacitance [8] (for all packages) Parameter Description C Input Capacitance IN C Output Capacitance OUT Thermal Resistance Parameter Description Θ Thermal Resistance JA (Junction to Ambient) Θ Thermal Resistance JC (Junction to Case) AC Test Loads and Waveforms R1 V ...

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... HZOE HZCE HZWE 13. The internal write time of the memory is defined by the overlap of WE terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 14. Device is continuously selected HIGH for read cycle. ...

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Switching Waveforms (continued) [15, 16] Read Cycle No. 2 (OE Controlled) ADDRESS HIGH IMPEDANCE DATA OUT t LZCE SUPPLY CURRENT [17, 18] Write Cycle No. 1 (WE Controlled) ADDRESS ...

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Switching Waveforms (continued) [17, 18] Write Cycle No. 2 (CE Controlled) ADDRESS DATA IO Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS NOTE 19 DATA IO t HZWE Truth Table CE WE ...

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... Ordering Information Speed (ns) Ordering Code 55 CY62148DV30LL-55BVI CY62148DV30LL-55BVXI CY62148DV30L-55ZSXI CY62148DV30LL-55ZSXI CY62148DV30LL-55SXI 70 CY62148DV30LL-70ZSXI CY62148DV30LL-70ZSXA 51-85095 32-pin TSOP II (Pb-free) Contact your local Cypress sales representative for availability of these parts Package Diagrams TOP VIEW A1 CORNER 6.00±0.10 SEATING PLANE C Document #: 38-05341 Rev. *D Package Diagram Package Type 51-85149 36-ball VFBGA (6 × ...

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... Document #: 38-05341 Rev. *D © Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

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Document History Page Document Title:CY62148DV30, 4-Mbit (512K x 8) MoBL Document Number: 38-05341 Issue REV. ECN NO. Date ** 127480 06/17/03 *A 131041 01/23/04 *B 222180 See ECN *C 498575 See ECN *D 729917 See ECN Document #: 38-05341 Rev. ...