CY7C1361C-100AXC Cypress Semiconductor Corp, CY7C1361C-100AXC Datasheet - Page 23

• Manufacturer Part Number: CY7C1361C-100AXC
• Description: IC SRAM 9MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1361C-100AXC

• Memory Size: 9M (256K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 8.5 ns
• Maximum Clock Frequency: 100 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 180 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2127; CY7C1361C-100AXC

Switching Characteristics
Over the Operating Range
Document Number: 38-05541 Rev. *J
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Set-up Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes
POWER
CYC
CH
CL
CDV
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ADS
ADVS
WES
DS
CES
AH
ADH
WEH
ADVH
DH
CEH
19. Timing reference level is 1.5 V when V
20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
21. This part has a voltage regulator internally; t
22. t
23. At any given voltage and temperature, t
24. This parameter is sampled and not 100% tested.
Parameter
can be initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve high Z prior to low Z under the same system conditions.
CHZ
, t
CLZ
,t
OELZ
, and t
OEHZ
V
Clock cycle time
Clock HIGH
Clock LOW
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z
Clock to high Z
OE LOW to output valid
OE LOW to output low Z
OE HIGH to output high Z
Address setup before CLK rise
ADSP, ADSC setup before CLK rise
ADV setup before CLK rise
GW, BWE, BW
Data input setup before CLK rise
Chip enable setup
Address hold after CLK rise
ADSP, ADSC hold after CLK rise
GW, BWE, BW
ADV hold after CLK rise
Data input hold after CLK rise
Chip enable hold after CLK rise
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
DD
[19, 20]
(Typical) to the first access
DDQ
OEHZ
POWER
= 3.3 V and is 1.25 V when V
[22, 23, 24]
is less than t
[22, 23, 24]
[A:D]
[A:D]
Description
is the time that the power needs to be supplied above V
setup before CLK rise
hold after CLK rise
OELZ
[22, 23, 24]
[22, 23, 24]
and t
[21]
CHZ
is less than t
DDQ
= 2.5 V.
CLZ
Min
7.5
3.0
3.0
2.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
to eliminate bus contention between SRAMs when sharing the same
1
–
0
–
–
0
–
–133
Max
6.5
3.5
3.5
3.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DD
(minimum) initially, before a read or write operation
CY7C1361C/CY7C1363C
Min
1.5
0.5
4.0
4.0
2.0
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
10
1
–
0
–
–
0
–
–100
Max
8.5
3.5
3.5
3.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 23 of 34
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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