CY7C1308DV25C-167BZC Cypress Semiconductor Corp, CY7C1308DV25C-167BZC Datasheet
CY7C1308DV25C-167BZC
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CY7C1308DV25C-167BZC Summary of contents
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... Document #: 001-04310 Rev. *A PRELIMINARY 9 Mbit DDR I SRAM 4-Word Functional Description The CY7C1308DV25C is a 2.5V Synchronous Pipelined SRAM equipped with DDR I (Double Data Rate) architecture. The DDR I architecture consists of an SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. Addresses for Read and Write are latched on alternate rising edges of the input (K) clock ...
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... Selection Guide Parameter Maximum Operating Frequency Maximum Operating Current Shaded areas contain advance information. Pin Configuration CY7C1308DV25C (256K × 36) – 11 × 15 FBGA GND/144M NC/36M B NC DQ18 DQ27 DQ28 D NC DQ29 DQ19 DQ20 F NC DQ30 DQ21 G NC DQ31 DQ22 REF DDQ J NC ...
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... K). Read Operations The CY7C1308DV25C is organized internally as an array of 256K x 36. Accesses are completed in a burst of four sequential 36-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the Positive Input Clock (K) ...
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... When deselected, the Write port ignores all inputs after the pending Write operations are completed. Single Clock Mode The CY7C1308DV25C can be used with a single clock that controls both the input and output registers. In this mode, the device recognizes only a single pair of input clocks (K and K) that control both the input and output registers ...
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... H Q(A1) at C(t+1)↑ High Previous State Previous State Previous State Previous State Third Address (Internal) X..X01 X..X10 X..X10 X..X11 X..X11 X..X00 X..X00 X..X01 ↑ represents rising edge. CY7C1308DV25C ZQ SRAM#2 DQ CQ/CQ 250ohms A LD# R/ D(A2) at D(A3) at D(A4) at K(t+2) ↑ K(t+2) ↑ K(t+1)↑ ...
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... V – 0.2V. IL REF Ω Ω /2)/(RQ/5) for values of 175 <= RQ <= 350 . Ω Ω <= RQ <= 350 . (Max.) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1308DV25C Ambient [11 DDQ ) A 0°C to +70°C 2.5 ± 0.1V 1.4V to 1.9V Min Typ Max 2.4 2.5 2.6 1 ...
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... Test Conditions T = 25° MHz 2. 1.5V DDQ V /2 DDQ 50Ω REF DDQ OUTPUT Device 0.25V 5 pF Under ZQ Test RQ = 250Ω INCLUDING JIG AND (b) SCOPE CY7C1308DV25C 165 FBGA Unit °C/W 16.7 °C/W 2.5 Max Unit [18] ALL INPUT PULSES 1.25V 0.75V Page [+] Feedback ...
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... AC test loads CY7C1308DV25C 200 MHz 167 MHz Unit Max Min Max Min Max μ – 5.0 – 6.0 ns – 2.0 – 2.4 ns – ...
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... In this example, if address A4 = A3, then data Q41 = D31, Q42 = D32, Q43 = D33, and Q44 = D34. Write data is forwarded immediately as Read results.This note applies to the whole diagram. Document #: 001-04310 Rev. *A PRELIMINARY is the time power needs to be supplied above V Power and, t less than t . CLZ CHZ CO CY7C1308DV25C minimum initially before a Read DD Page [+] Feedback ...
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... TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller needs to be moved into the Update-IR state. CY7C1308DV25C ) when SS Page [+] Feedback ...
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... Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1308DV25C Page [+] Feedback ...
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... IDLE Note 25. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 001-04310 Rev. *A PRELIMINARY [25] 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1308DV25C 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page [+] Feedback ...
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... TAP Controller [10, 12, 26] Over the Operating Range Test Conditions = −2 −100 μ 2 100 μ GND ≤ V ≤ DDQ [27, 28] Over the Operating Range Description / ns CY7C1308DV25C Selection TDO Circuitry Min Max Unit 1.7 V 2.1 V 0.7 V 0 –0.3 0.7 V μA –5 5 Min ...
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... TCK Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Document #: 001-04310 Rev. *A PRELIMINARY [27, 28] Over the Operating Range (continued) Description [28] ALL INPUT PULSES 2.5V 1.25V TMSS t TMSH t TDIS t TDIH t t TDOX TDOV CY7C1308DV25C Min Max Unit TCYC Page [+] Feedback ...
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... Version number. Defines the type of SRAM. Allows unique identification of SRAM vendor. 1 Indicate the presence register 107 Description Boundary Scan Order Bit # 11P 24 10P 25 10N 10M CY7C1308DV25C Description (continued) Bump ID 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H Page [+] Feedback ...
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... Boundary Scan Order (continued) Bit # Bump Internal Document #: 001-04310 Rev. *A PRELIMINARY Boundary Scan Order Bit # 10G 11F 72 11G 10F 75 11E 76 10E 77 10D 10C 80 11D 11B 84 11C 10B 87 11A 100 4A 101 5C 102 4B 103 3A 104 1H 105 1A 106 CY7C1308DV25C (continued) Bump Page [+] Feedback ...
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... Speed Ordering Code (MHz) 250 CY7C1308DV25C-250BZC 200 CY7C1308DV25C-200BZC 167 CY7C1308DV25C-167BZC Shaded areas contain advance information. Contact your local Cypress sales representative for availability of these parts. Package Diagram Figure 2. 165 FBGA 1.40 mm BB165D Document #: 001-04310 Rev. *A PRELIMINARY Package Name Package Type BB165D ...
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... Document History Page Document Title: CY7C1308DV25C 9 Mbit DDR I SRAM 4-Word Burst Architecture Document Number: 001-04310 Rev. ECN No. Submission Date ** 397842 See ECN *A 2748172 08/04/09 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...