CY7C1168V18-400BZC Cypress Semiconductor Corp, CY7C1168V18-400BZC Datasheet - Page 6

• Manufacturer Part Number: CY7C1168V18-400BZC
• Description: IC SRAM 18MBIT 400MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1168V18-400BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 18M (1M x 18)
• Speed: 400MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Definitions
Document Number: 001-06620 Rev. *D
DQ
LD
NWS
BWS
BWS
A
R/W
QVLD
K
K
CQ
CQ
Pin Name
[x:0]
0
2
0
, BWS
, BWS
, NWS
1
3
1
,
,
Input Output-
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input
Valid Output
Indicator
Input-
Input-
Input-
Input-
Input-
Input-
Clock
Input-
Clock
IO
Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid
write operations. These pins drive out the requested data when a read operation is active. Valid data
is driven out on the rising edge of both the K and K clocks during read operations. When read access
is deselected, Q[x:0] are automatically tri-stated.
CY7C1166V18 − DQ
CY7C1177V18 − DQ
CY7C1168V18 − DQ
CY7C1170V18 − DQ
Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined. This
definition includes address and read/write direction. All transactions operate on a burst of two data.
LD must meet the setup and hold times around edge of K. LD must meet the setup and hold times
around edge of K.
Nibble Write Select 0, 1 − Active LOW.(CY7C1166V18 Only) Sampled on the rising edge of the K
and K clocks during write operations. It is used to select the nibble that is written into the device
NWS
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write
Select ignores the corresponding nibble of data and not written into the device.
Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks
during Write operations. It is used to select the byte that is written into the device during the current
portion of the write operations. Bytes not written remain unaltered.
CY7C1177V18 − BWS
CY7C1168V18 − BWS
CY7C1170V18 − BWS
controls D
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and not written into the device.
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.
These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 2M x 8 (two arrays each of1M x 8) for CY7C1166V18, 2M x 9 (two arrays each of 1M
x 9) for CY7C1177V18, 1M x 18 (two arrays each of 512K x 18) for CY7C1168V18, and 512K x 36
(two arrays each of 256K x 18) for CY7C1170V18. All the address inputs are ignored when the
appropriate port is deselected.
Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read
when R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold
times around edge of K.
Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and
CQ.
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
edge of K.
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device
and to drive out data through Q
clock (K) of the DDR-II+. The timings for the echo clocks are shown in the
on page 22.
clock (K) of the DDR-II+. The timings for the echo clocks are shown in the
on page 22.
0
controls D
[35:27]
.
[3:0]
[7:0]
[8:0]
[17:0]
[35:0]
and NWS
0
0
0
controls D
controls D
controls D
[x:0]
1
[x:0]
controls D
[8:0],
[8:0]
when in single clock mode. All accesses are initiated on the rising
[8:0]
when in single clock mode.
, BWS
and BWS
Pin Description
[7:4]
1
controls D
.
1
controls D
CY7C1166V18, CY7C1177V18
CY7C1168V18, CY7C1170V18
[17:9]
[17:9].
, BWS
2
controls D
“Switching Characteristics”
“Switching Characteristics”
[26:18]
, and BWS
Page 6 of 27
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