CY7C1321CV18-167BZC Cypress Semiconductor Corp, CY7C1321CV18-167BZC Datasheet - Page 10

• Manufacturer Part Number: CY7C1321CV18-167BZC
• Description: IC SRAM 18MBIT 167MHZ 165LFBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1321CV18-167BZC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous, DDR II
• Memory Size: 18M (512K x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 165-LFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Application Example
Figure 1
Truth Table
The truth table for the CY7C1317CV18, CY7C1917CV18, CY7C1319CV18, and CY7C1321CV18 follows.
Notes
Document Number: 001-07161 Rev. *B
Write Cycle:
Load address; wait one cycle;
input write data on four consecutive K
and K rising edges.
Read Cycle:
Load address; wait one and a half cycle;
read data on four consecutive C and C
rising edges.
NOP: No Operation
Standby: Clock Stopped
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device powers up deselected with the outputs in a tri-state condition.
4. On CY7C1319CV18 and CY7C1321CV18, “A1” represents address location latched by the devices when transaction was initiated and “A2”, “A3”, “A4” represents the
5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
addresses sequence in the burst. On CY7C1317CV18 and CY7C1917CV18, “A1” represents A + ‘00’ and “A2” represents A + ‘01’, “A3” represents A + ‘10’ and “A4”
represents A + ‘11’.
symmetrically.
MASTER
ASIC)
(CPU
BUS
or
shows two DDR-II used in an application.
Operation
Source CLK#
Return CLK#
Cycle Start#
Return CLK
Source CLK
Addresses
R/W#
DQ
R = 50ohms
DQ
Vterm = 0.75V
Vterm = 0.75V
A
Stopped X
L-H
L-H
L-H
K
LD#
SRAM#1
R/W#
Figure 1. Application Example
LD R/W
H
L
L
C C#
H Q(A1) at C(t + 1)↑ Q(A2) at C(t + 2)↑ Q(A3) at C(t + 2)↑ Q(A4) at C(t + 3)↑
X High-Z
X Previous State
L D(A1) at K(t + 1)↑ D(A2) at K(t + 1)↑ D(A3) at K(t + 2)↑ D(A4) at K(t + 2)↑
CQ/CQ#
K
K#
ZQ
R = 250ohms
DQ
CY7C1317CV18, CY7C1917CV18
CY7C1319CV18, CY7C1321CV18
High-Z
Previous State
DQ
DQ
A
High-Z
Previous State
LD#
SRAM#2
R/W#
DQ
C C#
[2, 3, 4, 5, 6, 7]
CQ/CQ#
K
K#
High-Z
Previous State
ZQ
R = 250ohms
Page 10 of 31
DQ
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