MAX806TESA+ Maxim Integrated, MAX806TESA+ Datasheet - Page 8
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MAX806TESA+
Manufacturer Part Number
MAX806TESA+
Description
Supervisory Circuits
Manufacturer
Maxim Integrated
Series
MAX690R, MAX690S, MAX690T, MAX704R, MAX704S, MAX704T, MAX802, MAX802R, MAX802S, MAX802T, MAX804, MAX804R, MAX804S, MAX804T, MAX805, MAX805R, MAX805S, MAX805T, MAX806, MAX806R, MAX806S, MAX806Tr
Datasheet
1.MAX1662EUB.pdf
(11 pages)
Specifications of MAX806TESA+
Number Of Voltages Monitored
1
Monitored Voltage
1.1 V to 5.5 V
Undervoltage Threshold
3 V
Overvoltage Threshold
3.14 V
Output Type
Active Low, Push-Pull
Manual Reset
Resettable
Watchdog
No Watchdog
Battery Backup Switching
Backup
Power-up Reset Delay (typ)
200 ms
Supply Voltage - Max
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOIC-8 Narrow
Chip Enable Signals
No
Maximum Power Dissipation
471 mW
Minimum Operating Temperature
- 40 C
Power Fail Detection
Yes
Supply Current (typ)
50 uA
Supply Voltage - Min
1.1 V
Dual/Triple-Voltage
µP Supervisory Circuits
During the normal operating mode, the supervisor will
issue a reset pulse for the reset timeout period (140ms
min) if the µP does not update the WDI with a valid tran-
sition (HIGH to LOW or LOW to HIGH) within the stan-
dard timeout period (1.6s min).
After each reset event (V
watchdog reset), there is an initial watchdog startup
timeout period of 25.6s. The startup mode provides an
extended period for the system to power up and fully
initialize all µP and system components before assum-
ing responsibility for routine watchdog updates. The
normal watchdog timeout period (1.6s min) begins at
the conclusion of the startup timeout period or after the
first transition on WDI before the conclusion of the start-
up period (Figure 3).
In some systems, it is necessary to ensure a valid reset
even if V
cuit shown in Figure 4. Note that this configuration does
not work for the open-drain outputs of the MAX6352/
MAX6355/MAX6358.
Microprocessors with bidirectional reset pins will con-
tend with the push-pull outputs of these devices. To
prevent this, connect a 4.7kΩ resistor between RESET
and the µP’s reset I/O port, as shown in Figure 5. Buffer
RESET as shown in the figure if this reset is used by
other components in the system.
Figure 3. Normal Watchdog Startup Sequence
8
WDI
V
RESET
_______________________________________________________________________________________
CC
CC
falls to 0. In these applications, use the cir-
Ensuring a Valid
Applications Information
V
TH
140ms
t
WDI-NORMAL
t
1.6s MAX
WDI-STARTUP
Bidirectional Reset Pins
25.6s MAX
CC
Interfacing to µPs with
power-up, manual reset, or
Down to V
1.6s
MAX
RESET Output
CC
= 0
Figure 4. Ensuring a Valid Reset Low to V
Figure 5. Interfacing to µPs with Bidirectional Reset I/O
TRANSISTOR COUNT: 855
V
CC
2
V
CC
1
V
MAX6351–MAX6360
V
V
CC
CC
CC
2
1
2
V
GND
CC
1
RST2
RST1
RST
V
V
MAX6351 MAX6356
MAX6353 MAX6357
MAX6354 MAX6359
CC
CC
BUFFERED RESET TO OTHER SYSTEM COMPONENTS
1
2
Chip Information
4.7kΩ
GND
MAX6360
RST2
RST1
RST
CC
1 and V
RESET
GND
µP
CC
100kΩ
2 = 0