IDT70V28L15PFG IDT, Integrated Device Technology Inc, IDT70V28L15PFG Datasheet

IC SRAM 1MBIT 15NS 100TQFP

IDT70V28L15PFG

Manufacturer Part Number
IDT70V28L15PFG
Description
IC SRAM 1MBIT 15NS 100TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of IDT70V28L15PFG

Format - Memory
RAM
Memory Type
SRAM - Dual Port, Asynchronous
Memory Size
1M (64K x 16)
Speed
15ns
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Density
1Mb
Access Time (max)
15ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3.3V
Address Bus
16b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
235mA
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
16b
Number Of Words
64K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
70V28L15PFG
800-1393

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT70V28L15PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT70V28L15PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT70V28L15PFGI
Manufacturer:
THOMBETT
Quantity:
3 072
©2008 Integrated Device Technology, Inc.
Features
Functional Block Diagram
NOTES:
1. BUSY is an input as a Slave (M/S=V
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 15/20ns (max.)
– Industrial: 20ns (max.)
Low-power operation
– IDT70V28L
Dual chip enables allow for depth expansion without
external logic
IDT70V28 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading more
than one device
I/O
Active: 440mW (typ.)
Standby: 660µW (typ.)
BUSY
I/O
SEM
R/
CE
CE
8-15L
INT
A
OE
UB
LB
0-7L
A
15L
W
0L
0L
1L
L
L
L
L
L
L
L
(1,2)
(2)
IL
Decoder
Address
) and an output when it is a Master (M/S=V
R/W
CE
CE
OE
0L
1L
L
L
16
Control
I/O
HIGH-SPEED 3.3V
64K x 16 DUAL-PORT
STATIC RAM
ARBITRATION
SEMAPHORE
INTERRUPT
MEMORY
ARRAY
64Kx16
70V28
LOGIC
M/S
IH
1
).
(1)
M/S = V
M/S = V
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate upper-byte and lower-byte controls for multi-
plexed bus and bus matching compatibility
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Control
I/O
IL
IH
for BUSY input on Slave
for BUSY output flag on Master,
16
Decoder
Address
CE
CE
OE
R/W
0R
1R
R
R
OCTOBER 2008
4849 drw 01
IDT70V28L
R/
UB
CE
CE
OE
LB
BUSY
A
A
SEM
INT
I/O
I/O
15R
0R
W
R
R
0R
1R
R
R
R
8-15R
0-7R
R
(2)
DSC-4849/5
R
(1,2)

Related parts for IDT70V28L15PFG

IDT70V28L15PFG Summary of contents

Page 1

... Features True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 15/20ns (max.) – Industrial: 20ns (max.) Low-power operation – IDT70V28L Active: 440mW (typ.) Standby: 660µW (typ.) Dual chip enables allow for depth expansion without ...

Page 2

... This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. Industrial and Commercial Temperature Ranges for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (either CE permit the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’ ...

Page 3

IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Pin Names Left Port Right Port Chip Enables R/W R/W Read/Write Enable Output Enable ...

Page 4

IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Truth Table I – Chip Enable < 0. >V -0.2V CC (3) X NOTES: 1. Chip Enable references are shown above ...

Page 5

IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter ( Input Leakage Current Output Leakage Current LO V Output Low Voltage OL ...

Page 6

IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM AC Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load Waveform of Read Cycles ADDR ( UB, LB R/W DATA OUT ...

Page 7

IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA (3) t Chip Enable Access Time ACE ...

Page 8

... and a R for memory array writing cycle transition, the outputs remain in the High-impedance state. IL during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the IH and SEM = Industrial and Commercial Temperature Ranges (1,5,8) ...

Page 9

IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS t AW SEM I R/W OE NOTES ...

Page 10

IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (M/S BUSY Access Time from Address Match t BAA BUSY Disable Time from Address Not ...

Page 11

IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Timing Waveform of Write with Port-to-Port Read and BUSY (M ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES: 1. ...

Page 12

IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing (M ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled by ...

Page 13

IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" CE "A" R/W "A" INT "B" ADDR "B" CE "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and right ...

Page 14

... FFFE or FFFF is user-defined since addressable SRAM location. If the interrupt function is not used, address locations FFFE and FFFF are not used as mail boxes, but as part of the random access memory. Refer to Truth Table IV for the interrupt operation. 14 Industrial and Commercial Temperature Ranges outputs can not be LOW simultaneously ...

Page 15

IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses ...

Page 16

... The eight semaphore flags reside within the IDT70V28 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a low input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, CE, and R/W) as they would be used in accessing a standard Static RAM ...

Page 17

IDT70V28L High-Speed 3.3V 64K x 16 Dual-Port Static RAM Ordering Information XXXXX A 999 Device Power Speed Package Type NOTE: 1. Contact your sales office for Industrial Temperature range in other speeds, packages and powers. 2. Green parts available. For ...

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