ST72T331N2T6 STMicroelectronics, ST72T331N2T6 Datasheet - Page 34

• Manufacturer Part Number: ST72T331N2T6
• Description: 8-bit Microcontrollers - MCU OTP EPROM 8K SPI/SCI
• Manufacturer: STMicroelectronics

Specifications of ST72T331N2T6

• Product Category: 8-bit Microcontrollers - MCU
• Rohs: yes
• Core: ST7
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 16 MHz
• Program Memory Size: 8 KB
• Data Ram Size: 384 B
• On-chip Adc: Yes
• Package / Case: TQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 8 bit
• A/d Channels Available: 8
• Interface Type: SCI, SPI
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 44
• Number Of Timers: 2
• On-chip Dac: No
• Program Memory Type: EPROM
• Factory Pack Quantity: 90
• Supply Voltage - Max: 5.5 V
• Supply Voltage - Min: 3.5 V

ST72E331 ST72T331
EEPROM (Cont’d)
5.2.3 Functional description
5.2.3.1 Read operation (E2LAT=0)
The EEPROM can be read as a normal ROM loca-
tion when the E2LAT bit of the CR register is
cleared. In a read cycle, the desired byte is put on
the data bus in less than 1 CPU clock cycle. This
means that reading data from EEPROM takes the
same time as reading data from EPROM, but this
memory cannot be used to execute machine code.
5.2.3.2 Write operation (E2LAT=1)
The EEPROM programming flowchart is shown in
Figure
To access write mode set the E2LAT bit, the
E2PGM bit stays cleared. Then when a write ac-
cess to the EEPROM occurs, the value on the data
bus is latched on the 16 data latches depending
on the address.
When E2PGM is set, all the previous bytes written
(1 up to 16) are programmed in the EEPROM
cells. The effective high address (row) is deter-
mined by the last EEPROM write sequence. To
avoid wrong programming, the user must take
care that all the bytes written between two pro-
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24.
gramming sequences have the same high ad-
dress: only the four Least Significant Bits of the ad-
dress can change.
At the end of the cycle, the E2PGM and E2LAT
bits are cleared simultaneously, and an interrupt is
generated if the E2ITE bit is set.
Note: Care should be taken during the program-
ming cycle. Writing to the same memory location
will over-program the memory (logical AND be-
tween the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of
E2LAT bit.
It is not possible to read the latched data.
5.2.3.3 EEPROM Access Error handling
If a read access occurs while E2LAT=1, then the
data bus will not be driven.
If a write access occurs while E2LAT=0, then the
data on the bus will not be latched.
If a programming cycle is interrupted (by software/
RESET action), the memory data will not be guar-
anteed.