93LC86AT-I/OT Microchip Technology, 93LC86AT-I/OT Datasheet - Page 10
![IC EEPROM 16KBIT 3MHZ SOT23-6](/photos/6/59/65928/sot-23-6_pkg_sml.jpg)
93LC86AT-I/OT
Manufacturer Part Number
93LC86AT-I/OT
Description
IC EEPROM 16KBIT 3MHZ SOT23-6
Manufacturer
Microchip Technology
Specifications of 93LC86AT-I/OT
Memory Size
16K (2K x 8)
Package / Case
SOT-23-6
Operating Temperature
-40°C ~ 85°C
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
3MHz
Interface
Microwire, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Organization
2 K x 8
Interface Type
Microwire
Maximum Clock Frequency
2 MHz
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
3 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
2.5 V, 5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
93LC86AT-I/OT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
93LC86AT-I/OT
Manufacturer:
TI
Quantity:
1 122
Part Number:
93LC86AT-I/OT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
93AA86A/B/C, 93LC86A/B/C, 93C86A/B/C
2.9
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
The self-timed auto-erase and programming cycle is
initiated by the rising edge of CLK on the last data bit.
Clocking of the CLK pin is not necessary after the
device has entered the WRAL cycle. The WRAL
command does include an automatic ERAL cycle for
the device. Therefore, the WRAL instruction does not
require an ERAL instruction, but the chip must be in the
EWEN status.
FIGURE 2-7:
DS21797J-page 10
CLK
DO
CS
DI
Write All (WRAL)
1
High-Z
WRAL TIMING
0
0
0
1
x
•••
x
The DO pin indicates the Ready/
device if CS is brought high after a minimum of 250 ns
low (T
V
Dx
CC
Note:
Note:
must be ≥4.5V for proper operation of WRAL.
CSL
•••
).
D0
The write sequence requires a logic high
signal on the PE pin prior to the rising
edge of the last data bit.
After the Write All cycle is complete,
issuing a Start bit and then taking CS low
will clear the Ready/
T
CSL
T
WL
Busy
© 2008 Microchip Technology Inc.
T
SV
Ready
Busy
Busy
H
status from DO.
IGH
T
status of the
-Z
CZ