DS1245WP-150+ Maxim Integrated Products, DS1245WP-150+ Datasheet - Page 8

• Manufacturer Part Number: DS1245WP-150+
• Description: IC NVSRAM 1MBIT 150NS 34PCM
• Manufacturer: Maxim Integrated Products

Specifications of DS1245WP-150+

• Format - Memory: RAM
• Memory Type: NVSRAM (Non-Volatile SRAM)
• Memory Size: 1M (128K x 8)
• Speed: 150ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 34-PowerCap™ Module
• Data Bus Width: 8 bit
• Organization: 128 K x 8
• Interface Type: Parallel
• Access Time: 150 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Operating Current: 50 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER-DOWN/POWER-UP TIMING
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery
backup mode.
NOTES:
1.
2.
3. t
4. t
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the
7. If the
8. If
9. Each DS1245W has a built-in switch that disconnects the lithium source until V
10. All AC and DC electrical characteristics are valid over the full operating temperature range. For
11. In a power-down condition the voltage on any pin may not exceed the voltage on V
12. t
13. t
14. DS1245 modules are recognized by Underwriters Laboratories (UL) under file E99151.
PARAMETER
V
V
V
V
V
PARAMETER
Expected Data Retention Time
CC
CC
CC
CC
CC
going low to the earlier of
buffers remain in a high impedance state during this period.
buffers remain in high impedance state during this period.
the output buffers remain in a high impedance state during this period.
the user. The expected t
time power is first applied by the user.
commercial products, this range is 0°C to 70°C. For industrial products (IND), this range is -40°C to
+85°C.
WE
OE
WP
DH
WR1
WR2
Fail Detect to
slew from V
slew from 0V to V
Valid to
Valid to End of Write Protection
WE
, t
is specified as the logical AND of
= V
is high for a Read Cycle.
and t
and t
DS
CE
CE
is low or the
are measured from the earlier of
IH
DH1
DH2
or V
low transition occurs simultaneously with or latter than the
CE
high transition occurs prior to or simultaneously with the
are measured from
are measured from
TP
and
IL
. If
CE
to 0V
WE
OE
and
TP
WE
Inactive
= V
DR
WE
low transition occurs prior to or simultaneously with the
CE
IH
is defined as accumulative time in the absence of V
Inactive
during write cycle, the output buffers remain in a high impedance state.
or
CE
WE
WE
going high.
going high.
going high.
SYMBOL
SYMBOL
CE
CE
t
t
t
t
REC
or
t
and
t
PD
PU
DR
F
R
8 of 10
WE
WE
going high.
. t
MIN
MIN
150
150
WP
10
is measured from the latter of
TYP
TYP
WE
WE
MAX
MAX
125
1.5
15
2
high transition, the output
low transition, the output
(T
CC
A
CC
UNITS
UNITS
: See Note 10)
CC
CE
years
is first applied by
ms
ms
ms
starting from the
(T
µs
µs
.
low transition,
A
= +25°C)
CE
NOTES
NOTES
DS1245W
or
11
9
WE