ZLF645E0H2864G00TR Maxim Integrated, ZLF645E0H2864G00TR Datasheet - Page 149

• Manufacturer Part Number: ZLF645E0H2864G00TR
• Description: 8-bit Microcontrollers - MCU Crimzon Flash Infrared MCU
• Manufacturer: Maxim Integrated

Specifications of ZLF645E0H2864G00TR

• Core: Z8
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Operating Supply Voltage: 2 V to 3.6 V
• Package / Case: SSOP-28
• Mounting Style: SMD/SMT
• Interface Type: UART
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Number Of Programmable I/os: 5
• Number Of Timers: 2 x 8 bit, 1 x 16 bit
• Processor Series: ZLF645
• Program Memory Type: Flash

19-4572; Rev 0; 4/09
Bit Position
[1] 
[0] 
Power-On Reset Timer
Watchdog Timer
Caution:
When power is initially applied to the device, a timer circuit clocked by a dedicated 
on-board RC-oscillator provides the POR timer function. The POR timer circuit is a one-
shot timer that keeps the internal reset signal asserted long enough for V
oscillator circuit to stabilize before instruction execution begins.
The reset timer is triggered by one the following conditions:
•
•
•
SMR[5] can be cleared to 0 to bypass the POR timer on a Stop Mode Recovery. This must
only be done when using an external clock that does not require a startup delay.
The Watchdog Timer (WDT) is a retriggerable one-shot timer that resets the Z8 LXMC
CPU if it reaches its terminal count. The WDT must initially be enabled by executing the
WDT instruction. On subsequent executions of the WDT instruction, the WDT is
refreshed. The WDT circuit is driven by an on-board RC-oscillator. The WDT instruction
affects the Zero (Z), Sign (S), and Overflow (V) flags.
The POR clock source is an internal RC-oscillator. Bits 0 and 1 of the WDT register 
control a tap circuit that determines the minimum time-out period. Bit 2 determines
whether the WDT is active during HALT, and bit 3 determines WDT activity during STOP
mode. Bits 4 through 7 are reserved (see
only during the first 60 processor cycles (120 XTAL clocks) from the execution of the first
instruction after power-on reset, watchdog timer Reset, or a Stop Mode Recovery (see
Stop Mode
Value
Failure of an application to provide a stable oscillating clock input to XTAL1 before the
end of the ZLF645’s POR period may result in an indeterminate chip behavior and must
be avoided. For details on the POR timing range, see
Electrical Characteristics
Initial power-on or recovery from a VBO/standby condition.
Stop Mode Recovery (if register bit SMR[5] = 1).
Watchdog Timer time-out.
0
1
0
1
Description
LVD clear.
Low-voltage detected (V
Voltage detection disabled.
Voltage detection enabled.
Recovery). After this point, the register cannot be modified by any means. The
chapter.
DD
<V
Table 68
LVD)
on page 142). This register is accessible
ZLF645 Series Flash MCUs
Table 81
Product Specification
Power-On Reset Timer
on page 169 in the
DD
and the 
Fast
141