34LC02-E/ST Microchip Technology, 34LC02-E/ST Datasheet - Page 12
![IC EEPROM 2KBIT 1MHZ 8TSSOP](/photos/6/59/65937/c04-086_st_sml.jpg)
34LC02-E/ST
Manufacturer Part Number
34LC02-E/ST
Description
IC EEPROM 2KBIT 1MHZ 8TSSOP
Manufacturer
Microchip Technology
Specifications of 34LC02-E/ST
Memory Size
2K (256 x 8)
Package / Case
8-TSSOP
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
1MHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.2 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Organization
256 K x 8
Interface Type
I2C
Maximum Clock Frequency
1 MHz
Access Time
400 ns
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.2 V
Maximum Operating Current
3 mA
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
2.5 V, 3.3 V, 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
34LC02-E/ST
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
34AA02/34LC02
7.0
The 34XX02 has two software write-protect features
(SWP and PSWP) that allows the lower half of the array
(addresses 00h-7Fh) to be write-protected, as well as
a WP pin that can be used to protect the entire array.
The permanent software write-protect feature is
enabled by sending the device a special command.
Once this feature has been enabled, it cannot be
reversed. The resettable software write-protect feature
is also enabled by sending the device a special
command but can be reset by issuing another special
command. In addition to the software protect features,
there is a WP pin that can be used to write-protect the
entire array, regardless of whether the software write-
protect register has been written or not.
Table 7-2 and Table 7-3 describe how the 34XX02 will
acknowledge specific commands under various
circumstances.
7.1
The WP pin allows the user to write-protect the entire
array (00-FF) when the pin is tied to V
tied to V
FIGURE 7-1:
DS22029D-page 12
SS
WRITE PROTECTION
Hardware Write Protection
the write protection is disabled.
SOFTWARE WRITE PROTECTION FOR SWP, CSWP, PSWP, OR CPSWP
Bus Activity
Master
SDA Line
Bus Activity
CC
S 0 1 1 0
S
T
A
R
T
. If the pin is
Control
Byte
A
2
A
1
A
0
0
A
C
K
“Don’t Care”
Address
7.2
In addition to hardware write-protect the 34XX02 has
an additional software write-protect feature that, when
set, protects the first 128 bytes (00-7Fh) of the array
from being written.
Setting the software write protection is done by sending
the SWP instruction. SWP can also then be cleared by
issuing a CSWP instruction (see Figure 7-1).
These two instructions follow the same format as the
BYTE
Device Type Identifier, (typically ‘1010’, instead
changes to ‘0110’). Once this identifier is recognized
by the device, the rest of the Byte Write command,
address and data, are “don’t cares”. In addition to the
identifier, high voltage must be applied to the A0 pin of
the device and specific levels must be present on A1
and A2. See Table 7-1 for the available commands.
7.3
The Permanent software write protection, or PSWP is
another instruction that may be used to permanently
protect the first 128 byte of the array. Once this
command is issued, the user will no longer have the
ability to clear this feature regardless of instruction,
power cycling, or state of the WP pin. Also, once this
instruction has been executed, the device will no
longer acknowledge the device identifier ‘0110’.
Byte
WRITE instruction with the exception of the
Software Write Protection (SWP)
and Clear Software Write
Protection (CSWP)
Permanent Software Write-Protect
(PSWP)
A
C
K
“Don’t Care”
Data
© 2008 Microchip Technology Inc.
A
C
K
S
T
O
P
P