24LC21-I/SN Microchip Technology, 24LC21-I/SN Datasheet - Page 4

• Manufacturer Part Number: 24LC21-I/SN
• Description: IC EEPROM 1KBIT 400KHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 24LC21-I/SN

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 1K (128 x 8)
• Speed: 100kHz, 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24LC21
2.0
The 24LC21 operates in two modes, the Transmit-only
mode and the Bidirectional mode. There is a separate
two wire protocol to support each mode, each having a
separate clock input and sharing a common data line
(SDA). The device enters the Transmit-only mode upon
power-up. In this mode, the device transmits data bits
on the SDA pin in response to a clock signal on the
V
valid high-to-low transition is placed on the SCL input.
When a valid transition on SCL is recognized, the
device will switch into the Bidirectional mode. The only
way to switch the device back to the Transmit-only
mode is to remove power from the device.
2.1
The device will power-up in the Transmit-only mode.
This mode supports a unidirectional two wire protocol
for transmission of the contents of the memory array.
This device requires that it be initialized prior to valid
data being sent in the Transmit-only mode (see Initial-
ization Procedure, below). In this mode, data is trans-
FIGURE 2-1:
FIGURE 2-2:
DS21095J-page 4
CLK
pin. The device will remain in this mode until a
V
V
SDA
SCL
V
CLK
SDA
CLK
FUNCTIONAL DESCRIPTION
Transmit-only Mode
SCL
CC
TRANSMIT-ONLY MODE
DEVICE INITIALIZATION
T
High-impedance for 9 clock cycles
VAA
T
T
1
VHIGH
VPU
Bit 1 (LSB)
T
VLOW
2
T
VAA
Null Bit
mitted on the SDA pin in 8-bit bytes, each followed by
a ninth, null bit (see Figure 2-1). The clock source for
the Transmit-only mode is provided on the V
and a data bit is output on the rising edge on this pin.
The eight bits in each byte are transmitted Most Signif-
icant bit first. Each byte within the memory array will be
output in sequence. When the last byte in the memory
array is transmitted, the output will wrap around to the
first location and continue. The Bidirectional mode
Clock (SCL) pin must be held high for the device to
remain in the Transmit-only mode.
2.2
After V
mit-only mode. Nine clock cycles on the V
be given to the device for it to perform internal synchro-
nization. During this period, the SDA pin will be in a
high-impedance state. On the rising edge of the tenth
clock cycle, the device will output the first valid data bit
which will be the Most Significant bit of a byte. The
device will power-up at an indeterminate byte address.
(Figure 2-2).
8
CC
Initialization Procedure
has stabilized, the device will be in the Trans-
9
Bit 1 (MSB)
T
 2004 Microchip Technology Inc.
VAA
10
Bit 8
T
VAA
11
Bit 7
CLK
Bit 7
pin must
CLK
pin,