24LC21A/SN Microchip Technology, 24LC21A/SN Datasheet
24LC21A/SN
Specifications of 24LC21A/SN
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24LC21A/SN Summary of contents
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... Industrial (I): -40°C to +85°C Description The Microchip Technology Inc. 24LC21A is a 128 x 8-bit dual-mode Electrically Erasable PROM. This device is designed for use in applications requiring storage and serial transmission of configuration and control informa- tion. Two modes of operation have been implemented: Transmit-only mode and Bidirectional mode ...
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... Write — Read — — CCS — 100 A 0. +1. Conditions V 2.7V (Note < 2.7V (Note) CC (Note mA 2.5V (Note OUT 5.0V (Note MHz A CLK 5.5V, SCL = 400 kHz 3.0V, SDA = SCL = 5.5V, SDA = SCL = CLK SS 2003 Microchip Technology Inc. ...
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... This eliminates the need for This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from our web site. 2003 Microchip Technology Inc. Vcc= 2.5-5.5V Vcc= 4.5 - 5.5V Standard Mode ...
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... On the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the Most Significant bit in address 00h. (Figure 2-2). Tvaa Null Bit Bit 1 (MSB) Tvlow Bit 7 Tvaa Tvaa Bit 8 Bit 2003 Microchip Technology Inc. ...
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... SDA VCLK count = 1 2 VCLK 2003 Microchip Technology Inc. Once the device has switched into the Bidirectional mode, the VCLK input is disregarded, with the exception that a logic high level is required to enable write capability. This mode supports a two-wire Bidirectional data transmission protocol (I ...
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... VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA. 2: The dash box and text “The 24LC21A and... inside dash box.” are added by Microchip Technology Inc. 3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LC21A. ...
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... SCL SDA START CONDITION 2003 Microchip Technology Inc. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is theoretically unlimited, although only the last eight will be stored when doing a write operation ...
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... Acknowledge bit if the slave address was true and it is not in a programming mode. Operation Slave Address Read 1010000 Write 1010000 DS21160F-page 8 V HYS : STA T HIGH DAT SU DAT T AA FIGURE 3-7: START generates R STO STOP STO T BUF CONTROL BYTE ALLOCATION READ/WRITE R/W A SLAVE ADDRESS 2003 Microchip Technology Inc. ...
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... Note, however, that the VCLK is ignored during the self-timed program operation. Changing VCLK from high-to-low during the self-timed program operation will not halt programming of the device. 2003 Microchip Technology Inc. 24LC21A 4.2 Page Write The write control byte, word address and the first data byte are transmitted to the 24LC21A in the same way byte write ...
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... VCLK WRITE ENABLE TIMING SCL SDA IN VCLK T VHST FIGURE 4-3: PAGE WRITE S T BUS ACTIVITY A CONTROL MASTER R BYTE T SDA LINE BUS ACTIVITY K VCLK DS21160F-page 10 CONTROL WORD BYTE ADDRESS STA HD STO WORD DATA ADDRESS DATA ( DATA SPVL DATA 2003 Microchip Technology Inc. ...
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... Did Device No Acknowledge (ACK = 0)? Yes Next Operation 2003 Microchip Technology Inc. 24LC21A 6.0 WRITE PROTECTION When using the 24LC21A in the Bidirectional mode, the VCLK pin can be used as a write-protect control pin. Setting VCLK high allows normal write operations, while setting VCLK low prevents writing to any location in the array ...
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... V is below 1.5 volts at nominal conditions. The SDA, SCL and VCLK inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus DATA threshold detector circuit CC CC 2003 Microchip Technology Inc. ...
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... FIGURE 7-2: RANDOM READ BUS ACTIVITY CONTROL R MASTER BYTE T SDA LINE BUS ACTIVITY FIGURE 7-3: SEQUENTIAL READ BUS ACTIVITY MASTER CONTROL DATA n BYTE SDA LINE BUS ACTIVITY 2003 Microchip Technology Inc WORD CONTROL R ADDRESS BYTE DATA n+2 DATA n 24LC21A S T DATA n ...
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... VCLK This pin is the clock input for the Transmit-only mode (DDC1). In the Transmit-only mode, each bit is clocked out on the rising edge of this signal. In the Bidirectional mode, a high logic level is required on this pin to enable write capability. DS21160F-page 14 2003 Microchip Technology Inc. ...
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... APPENDIX A: REVISION HISTORY Revision F Corrections to Section 1.0, Electrical Characteristics. 2003 Microchip Technology Inc. 24LC21A DS21160F-page 15 ...
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... The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. DS21160F-page 16 XXX Pattern . 2003 Microchip Technology Inc. ...
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... Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system ...
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... Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands Biesbosch 14 NL-5152 SC Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 United Kingdom 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 07/28/03 2003 Microchip Technology Inc. ...