25C040-E/SN Microchip Technology, 25C040-E/SN Datasheet - Page 10

• Manufacturer Part Number: 25C040-E/SN
• Description: IC EEPROM 4KBIT 3MHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 25C040-E/SN

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8)
• Speed: 3MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25AA040/25LC040/25C040
3.5
The RDSR instruction provides access to the STATUS
register. The STATUS register may be read at any time,
even during a write cycle. The STATUS register is
formatted as follows:
The Write-In-Process (WIP) bit indicates whether the
25XX040 is busy with a write operation. When set to a
‘
in progress. This bit is read-only.
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘
allows writes to the array, when set to a ‘
prohibits writes to the array. The state of this bit can
always be updated via the WREN or WRDI commands
regardless of the state of write protection on the
STATUS register. This bit is read-only.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile.
See Figure 3-6 for RDSR timing sequence.
FIGURE 3-6:
FIGURE 3-7:
DS21204E-page 10
1
X
7
’, a write is in progress, when set to a ‘
6
X
Read Status Register (RDSR)
X
5
X
SCK
SCK
4
CS
SO
CS
SO
SI
SI
BP1
3
READ STATUS REGISTER SEQUENCE
WRITE STATUS REGISTER SEQUENCE
0
0
0
0
BP0
0
0
2
1
1
High-impedance
0
0
Instruction
Instruction
2
2
WEL
0
0
1
0
3
3
1
0
’, no write is
’, the latch
’, the latch
0
0
4
4
WIP
1
0
0
5
5
High-impedance
0
0
6
6
1
1
7
7
7
7
8
8
3.6
The WRSR instruction allows the user to select one of
four levels of protection for the array by writing to the
appropriate bits in the STATUS register. The array is
divided up into four segments. The user has the ability
to write-protect none, one, two, or all four of the
segments of the array. The partitioning is controlled as
illustrated in Table 3-2.
See Figure 3-7 for WRSR timing sequence.
TABLE 3-2:
6
6
9
Data from STATUS register
9
BP1
Data to STATUS register
0
0
1
1
10
10
5
5
Write Status Register (WRSR)
11
11
4
4
12
3
12
3
ARRAY PROTECTION
BP0
0
1
0
1
13
2
13
2
© 2006 Microchip Technology Inc.
14
14
1
1
15
0
15
0
Array Addresses
Write-Protected
(0180h-01FFh)
(0100h-01FFh)
(0000h-01FFh)
upper 1/4
upper 1/2
none
all