AT25DF021-SSHF-B Atmel, AT25DF021-SSHF-B Datasheet

Page 1

... Ultra Thin DFN ( 0.6 mm) 1. Description The AT25DF021 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shad- owed from Flash memory into embedded or external RAM for execution. The flexible ...

Page 2

... The physical sectoring and the erase block sizes of the AT25DF021 have been optimized to meet the needs of today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced ...

Page 3

Pin Descriptions and Pinouts Table 2-1. Pin Descriptions Symbol Name and Function CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in standby mode ...

Page 4

... HOLD 4. Memory Array To provide the greatest flexibility, the memory array of the AT25DF021 can be erased in four lev- els of granularity including a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which each sector can be individually protected from program and erase operations ...

Page 5

... Figure 4-1. Memory Architecture Diagram Internal Sectoring for 64KB Sector Protection Block Erase Function (D8h Command) (52h Command) (20h Command) 64KB 64KB (Sector 3) 64KB 64KB (Sector 2) 64KB 64KB (Sector 0) 3677D–DFLASH–04/09 Block Erase Detail 32KB 4KB Block Erase Block Erase ...

Page 6

... All opcode, address, and data bytes are trans- ferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin. Opcodes not supported by the AT25DF021 will be ignored by the device and no operation will be started. The device will continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and then reasserted) ...

Page 7

Table 6-1. Command Listing Command Read Commands Read Array Program and Erase Commands Block Erase (4 Kbytes) Block Erase (32 Kbytes) Block Erase (64 Kbytes) Chip Erase Byte/Page Program (1 to 256 Bytes) Protection Commands Write Enable Write Disable Protect ...

Page 8

... The CS pin can be deasserted at any time and does not require that a full byte of data be read. Figure 7-1. Read Array - 0Bh Opcode SCK OPCODE MSB HIGH-IMPEDANCE SO Figure 7-2. Read Array - 03h Opcode CS 0 SCK SI 0 MSB HIGH-IMPEDANCE SO AT25DF021 8 . RDLF ADDRESS BITS A23- MSB MSB ...

Page 9

... Status Register to a logical “1” state. To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device followed by the three address bytes denoting the first byte location of the memory array to begin programming at. After the address bytes have been clocked in, data can then be clocked into the device and will be stored in an internal buffer ...

Page 10

... Despite the lower order address bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the CS pin is deas- serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed. AT25DF021 ...

Page 11

... If the address specified by A23-A0 points to a memory location within a sector that is in the pro- tected state, then the Block Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an incomplete address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory location within the region to be erased is protected ...

Page 12

... CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not change. Figure 9-1. AT25DF021 12 time to determine if the device has finished erasing. At CHPE ...

Page 13

Write Disable The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Reg- ister to the logical “0” state. With the WEL bit reset, all Byte/Page Program, erase, Protect Sector, Unprotect Sector, ...

Page 14

... Sector Protection Register will be unchanged, and the WEL bit in the Status Register will be reset to a logical “0” safeguard against accidental or erroneous locking or unlocking of sectors, the Sector Pro- tection Registers can themselves be locked from updates by using the SPRL (Sector Protection AT25DF021 14 Protect Sector CS ...

Page 15

... Unprotect Sector command to individually unprotect certain sec- tors and individually reprotect them later by using the Protect Sector command. Likewise, a system can globally unprotect the entire memory array and then individually protect certain sec- tors as needed. ...

Page 16

... Global Protect. If the desire is to only change the SPRL bit without performing a Global Protect or Global Unpro- tect, then the system can simply write a 0Fh to the first byte of the Status Register to change the AT25DF021 16 Valid SPRL and Global Protect/Unprotect Conditions ...

Page 17

SPRL bit from a logical “1” logical “0” provided the WP pin is deasserted. Likewise, the sys- tem can write an F0h to change the SPRL bit from a logical “0” logical “1” without affecting the ...

Page 18

... Global Protect or Global Unprotect at the same time by writing the appropriate values into bits and 2 of the first byte of the Status Register. Tables 9-4 Table 9-4. (Don't Care) Note: AT25DF021 18 and 9-5 detail the various protection and locking states of the device. Sector Protection Register States Sector Protection Register ...

Page 19

... Once these 64 bytes have been programmed, they cannot be erased or reprogrammed. The remaining 64 bytes of the OTP Security Register (byte locations 64 through 127) are factory programmed by Atmel and will contain a unique value for each device. The factory programmed data is fixed and cannot be changed. ...

Page 20

... The Program OTP Security Register command utilizes the internal 256-buffer for processing. Therefore, the contents of the buffer will be altered from its previous state when this command is issued. AT25DF021 20 . OTPP time to determine if the data bytes have finished OTPP 3677D– ...

Page 21

Figure 10-1. Program OTP Security Register SCK OPCODE MSB HIGH-IMPEDANCE SO 10.2 Read OTP Security Register The OTP Security Register can be sequentially read in a similar fashion ...

Page 22

... WEL Write Enable Latch Status 0 RDY/BSY Ready/Busy Status Notes: 1. Only bit 7 of the Status Register will be modified when using the Write Status Register command. 2. R/W = Readable and writable R = Readable only AT25DF021 22 (2) Type Description 0 Sector Protection Registers are unlocked (default). R/W 1 Sector Protection Registers are locked ...

Page 23

SPRL Bit The SPRL bit is used to control whether the Sector Protection Registers can be modified or not. When the SPRL bit is in the logical “1” state, all Sector Protection Registers are locked and can- not be ...

Page 24

... To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data must be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical “1” logical “0”. Figure 11-1. Read Status Register SCK OPCODE MSB HIGH-IMPEDANCE SO AT25DF021 ATUS REGISTER ...

Page 25

Write Status Register The Write Status Register command is used to modify the SPRL bit of the Status Register and/or to perform a Global Protect or Global Unprotect operation. Before the Write Status Regis- ter command can be issued, ...

Page 26

... Device ID (Part 2) 4 Extended Device Information String Length Table 12-2. Manufacturer and Device ID Details Data Type Bit 7 Bit 6 Bit 5 Manufacturer Family Code Device ID (Part Sub Code Device ID (Part AT25DF021 26 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 JEDEC Assigned Code Density Code Product Version Code ...

Page 27

Figure 12-1. Read Manufacturer and Device ID CS SCK SO 12.2 Deep Power-Down During normal operation, the device will be placed in the standby mode to consume less power as long as the CS pin remains deasserted and no internal ...

Page 28

... If the complete opcode is not clocked in before the CS pin is deasserted the CS pin is not deasserted on an even byte boundary (multiples of eight bits), then the device will abort the operation and return to the Deep Power-Down mode. Figure 12-3. Resume from Deep Power-Down AT25DF021 ...

Page 29

Hold The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as ...

Page 30

... System Considerations In an effort to continue our goal of maintaining world-class quality leadership, Atmel has been performing extensive testing on the AT25DF021 that would not normally be done with a Serial Flash device. The testing that has been performed on the AT25DF021 involved extensive, non- stop reading of the memory array on pre-conditioned devices. The pre-conditioning of the devices, which entailed erasing and programming the entire memory array 10,000 times, was done to simulate a customer environment and to exercise the memory cells to a certain degree ...

Page 31

... CMOS levels MHz mA; OUT Max MHz mA; OUT Max MHz mA; OUT Max MHz mA; OUT Max MHz mA; OUT Max Max Max CMOS levels CMOS levels OUT AT25DF021 (2.7V Version) -40°C to 85°C 2.7V to 3.6V Typ Max Units 25 50 µ µ µA 1 µA 0 ...

Page 32

... CC CC AT25DF021 (2.3V Version) Min AT25DF021 (2.3V Version) Min 8.0 8.0 0.1 0 Typ Max Units CC 0.4 AT25DF021 (2.7V Version) Max Min Max Units AT25DF021 (2.7V Version) Max Min Max 6.4 6.4 0.1 0 3677D–DFLASH–04/ MHz MHz Units ns ns V/ns V/ns ...

Page 33

... Power-up Conditions Symbol Parameter t Minimum V to Chip Select Low Time VCSL CC t Power-up Device Delay Before Program or Erase Allowed PUW V Power-on Reset Voltage POR 3677D–DFLASH–04/09 AT25DF021 AT25DF021 (2.3V Version) (2.7V Version) Min Max Min 20 20 100 100 Min 4 Kbytes ...

Page 34

... Input Test Waveforms and Measurement Levels DRIVING LEVELS 14.9 Output Test Load AT25DF021 34 0. 0.1V CC < (10% to 90%) F DEVICE UNDER TEST 15 pF (frequencies above 66 MHz) or 30pF AC MEASUREMENT LEVEL 3677D–DFLASH–04/09 ...

Page 35

AC Waveforms Figure 15-1. Serial Input Timing CS t CSLS SCK MSB HIGH-IMPEDANCE SO Figure 15-2. Serial Output Timing CS SCK Figure 15-3. WP Timing for Write Status Register Command When SPRL ...

Page 36

... Figure 15-4. HOLD Timing – Serial Input CS SCK HOLD SI HIGH-IMPEDANCE SO Figure 15-5. HOLD Timing – Serial Output CS SCK t HHH HOLD SI t HLQZ SO AT25DF021 HHH HLS t HLH t HLS t HLH t HHQX t HHS t HHS 3677D–DFLASH–04/09 ...

Page 37

... Green Package Options (Pb/Halide-free/RoHS Compliant) Ordering Code Package AT25DF021-SSH-B 8S1 AT25DF021-SSH-T AT25DF021-MH-Y 8MA1 AT25DF021-MH-T AT25DF021-SSHF-B 8S1 AT25DF021-SSHF-T AT25DF021-MHF-Y 8MA1 AT25DF021-MHF-T Note: The shipping carrier option code is not marked on the devices. 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8MA1 8-pad ...

Page 38

... Packaging Information 17.1 8S1 – JEDEC SOIC TOP VIEW e e SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT25DF021 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing ...

Page 39

... UDFN E Pin TOP VIEW Pin #1 Notch (0.20 R) (Option BOTTOM VIEW L Package Drawing Contact: packagedrawings@atmel.com 3677D–DFLASH–04/09 A 0.45 Option A 1 Pin #1 Chamfer (C 0.35) SYMBOL TITLE 8MA1, 8-pad ( 0.6 mm Body), Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN) ...

Page 40

... Revision History Revision Level – Release Date A – February 2008 B – May 2008 C – September 2008 D – April 2009 AT25DF021 40 History Initial release Changed Deep Power-Down current specifications – Changed typical value from 4 µ µA – Changed maximum value from 8 µ µA Changed typical 64 KB Block Erase time from 400 ms to 450 ms Changed typical Chip Erase time from 1 ...

Page 41

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...