25LC080A-I/SN Microchip Technology, 25LC080A-I/SN Datasheet - Page 6

• Manufacturer Part Number: 25LC080A-I/SN
• Description: IC EEPROM 8KBIT 10MHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 25LC080A-I/SN

• Memory Size: 8K (1K x 8)
• Package / Case: 8-SOIC (3.9mm Width)
• Operating Temperature: -40°C ~ 85°C
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Organization: 1 K x 8
• Interface Type: SPI
• Maximum Clock Frequency: 10 MHz
• Access Time: 50 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

25XX080A/B
2.0
2.1
The 25XX080A/B are 1024 byte Serial EEPROMs
designed to interface directly with the Serial
Peripheral Interface (SPI) Port of many of today’s
popular
Microchip’s PIC
face with microcontrollers that do not have a built-in
Synchronous Serial Port by using discrete
I/O lines programmed properly with the software.
The 25XX080A/B contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSB first, LSB
last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25XX080A/B in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
2.2
The device is selected by pulling CS low. The 8-bit read
instruction is transmitted to the 25XX080A/B followed
by the 16-bit address, with the six MSBs of the address
being don’t care bits. After the correct read instruction
and address are sent, the data stored in the memory at
the selected address is shifted out on the SO pin. The
data stored in the memory at the next address can be
read sequentially by continuing to provide clock pulses.
The
incremented to the next higher address after each byte
of data is shifted out. When the highest address is
reached (03FFh), the address counter rolls over to
address 0000h allowing the read cycle to be continued
indefinitely. The read operation is terminated by raising
the CS pin (Figure 2-1).
DS21808D-page 6
internal
FUNCTIONAL DESCRIPTION
Principles of Operation
Read Sequence
microcontroller
®
address
microcontrollers. It may also inter-
pointer
families,
is
automatically
including
2.3
Prior to any attempt to write data to the 25XX080A/B,
the write enable latch must be set by issuing the WREN
instruction (Figure 2-4). This is done by setting CS low
and then clocking out the proper instruction into the
25XX080A/B. After all eight bits of the instruction are
transmitted, the CS must be brought high to set the
write enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.
Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a WRITE
instruction, followed by the 16-bit address, with the six
MSBs of the address being don’t care bits, and then the
data to be written. Up to 16 bytes (25XX080A) or 32
bytes (25XX080B) of data can be sent to the device
before a write cycle is necessary. The only restriction is
that all of the bytes must reside in the same page.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the n
brought high at any other time, the write operation will
not be completed. Refer to Figure 2-2 and Figure 2-3
for more detailed illustrations on the byte write
sequence and the page write sequence respectively.
While the write is in progress, the Status Register may
be read to check the status of the WPEN, WIP, WEL,
BP1 and BP0 bits (Figure 2-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.
Note:
th
Write Sequence
data byte has been clocked in. If CS is
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and, end at addresses that are
integer multiples of page size - 1. If a Page
Write command attempts to write across a
physical page boundary, the result is that
the data wraps around to the beginning of
the
previously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
current
© 2007 Microchip Technology Inc.
page
(overwriting
data