25LC080A-I/ST Microchip Technology, 25LC080A-I/ST Datasheet - Page 11

IC EEPROM 8KBIT 10MHZ 8TSSOP

25LC080A-I/ST

Manufacturer Part Number
25LC080A-I/ST
Description
IC EEPROM 8KBIT 10MHZ 8TSSOP
Manufacturer
Microchip Technology
Datasheet

Specifications of 25LC080A-I/ST

Memory Size
8K (1K x 8)
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
10MHz
Interface
SPI, 3-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-TSSOP
Memory Configuration
1K X 8 / 512 X 16
Ic Interface Type
SPI
Clock Frequency
10MHz
Supply Voltage Range
2.5V To 5.5V
Memory Case Style
TSSOP
No. Of Pins
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
25LC080A-I/ST
Manufacturer:
TI
Quantity:
7 588
Part Number:
25LC080A-I/ST
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
2.6
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the Status
Register as shown in Table 2-2. The user is able to
select one of four levels of protection for the array by
writing to the appropriate bits in the Status Register.
The array is divided up into four segments. The user
has the ability to write-protect none, one, two or all four
of the segments of the array. The partitioning is
controlled as shown in Table 2-3.
The Write-Protect Enable (WPEN) bit is also a
nonvolatile bit that is available as an enable bit for the WP
pin. The Write-Protect (WP) pin and the Write-Protect
Enable (WPEN) bit in the Status Register control the
programmable hardware write-protect feature. Hardware
write protection is enabled when WP pin is low and the
WPEN bit is high. Hardware write protection is disabled
when either the WP pin is high or the WPEN bit is low.
When the chip is hardware write-protected, only writes to
nonvolatile bits in the Status Register are disabled. See
Table 2-4 for a matrix of functionality on the WPEN bit.
FIGURE 2-7:
© 2007 Microchip Technology Inc.
SCK
CS
SO
SI
Write Status Register Instruction
(WRSR)
0
0
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
0
1
0
instruction
2
0
3
0
4
0
5
high-impedance
0
6
1
7
See Figure 2-7 for the WRSR timing sequence.
TABLE 2-3:
7
8
BP1
0
0
1
1
6
9
data to Status Register
10
5
11
4
ARRAY PROTECTION
BP0
0
1
0
1
25XX080A/B
12
3
13
2
Array Addresses
Write-Protected
(0300h - 03FFh)
(0200h - 03FFh)
(0000h - 03FFh)
14
upper 1/4
upper 1/2
1
DS21808D-page 11
none
all
15
0

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