24LC128-I/P Microchip Technology, 24LC128-I/P Datasheet - Page 8
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24LC128-I/P
Manufacturer Part Number
24LC128-I/P
Description
IC EEPROM 128KBIT 400KHZ 8DIP
Manufacturer
Microchip Technology
Specifications of 24LC128-I/P
Memory Size
128K (16K x 8)
Package / Case
8-DIP (0.300", 7.62mm)
Operating Temperature
-40°C ~ 85°C
Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.5 V ~ 5.5 V
Organization
16 K x 8
Interface Type
I2C
Maximum Clock Frequency
0.4 MHz
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.5 V
Maximum Operating Current
3 mA
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Operating Supply Voltage
5.5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
24LC128-I/P
Manufacturer:
MCP
Quantity:
11 132
Part Number:
24LC128-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
24AA128/24LC128/24FC128
6.0
6.1
Following the Start condition from the master, the
control code (four bits), the Chip Select (three bits) and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the address
pointer of the 24XX128. The next byte is the Least
Significant Address Byte. After receiving another
Acknowledge signal from the 24XX128, the master
device will transmit the data word to be written into the
addressed memory location. The 24XX128 acknowl-
edges again and the master generates a Stop
condition. This initiates the internal write cycle and
during this time, the 24XX128 will not generate
Acknowledge signals (Figure 6-1). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command, but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command. After a byte
Write command, the internal address counter will point
to the address location following the one that was just
written.
6.2
The write control byte, word address, and the first data
byte are transmitted to the 24XX128 in much the same
way as in a byte write. The exception is that instead of
generating a Stop condition, the master transmits up to
63 additional bytes, which are temporarily stored in the
on-chip page buffer, and will be written into memory
once the master has transmitted a Stop condition.
Upon receipt of each word, the six lower address
pointer bits are internally incremented by ‘
FIGURE 6-1:
FIGURE 6-2:
DS21191M-page 8
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
X = don’t care bit
WRITE OPERATIONS
Byte Write
Page Write
BUS ACTIVITY
X = don’t care bit
BUS ACTIVITY
MASTER
SDA LINE
BYTE WRITE
PAGE WRITE
S
T
A
R
T
S 1 0 1 0
Control
Byte
A
2
R
S
T
A
T
S 1 0 1 0
A
1
A
0
0
A
C
K
Control
Byte
X X
A
2
High Byte
A
1
Address
1
A
0
’. If the
0
A
C
K
X X
High Byte
Address
A
C
K
Low Byte
Address
master should transmit more than 64 bytes prior to
generating the Stop condition, the address counter will
roll over and the previously received data will be over-
written. As with the byte write operation, once the Stop
condition is received, an internal write cycle will begin
(Figure 6-2). If an attempt is made to write to the array
with the WP pin held high, the device will acknowledge
the command, but no write cycle will occur, no data will
be written and the device will immediately accept a new
command.
6.3
The WP pin allows the user to write-protect the entire
array (0000-3FFF) when the pin is tied to V
V
WP pin is sampled at the Stop bit for every Write
command (Figure 1-1). Toggling the WP pin after the
Stop bit will have no effect on the execution of the write
cycle.
SS
A
C
K
Note:
or left floating, the write protection is disabled. The
Low Byte
Address
A
C
K
Write-Protection
Data Byte 0
Page write operations are limited to
writing bytes within a single physical
page, regardless of the number of
bytes actually being written. Physical
page boundaries start at addresses
that are integer multiples of the page
buffer size (or ‘page size’) and end at
addresses that are integer multiples of
[page size - 1]. If a Page Write
command attempts to write across a
physical page boundary, the result is
that the data wraps around to the
beginning of the current page (over-
writing data previously stored there),
instead of being written to the next
page, as might be expected. It is,
therefore, necessary for the applica-
tion software to prevent page write
operations that would attempt to cross
a page boundary.
A
C
K
A
C
K
2004 Microchip Technology Inc.
Data
Data Byte 63
A
C
K
S
O
P
P
T
CC
A
C
K
S
T
O
P
P
. If tied to