AT25DF041A-MHF-T Atmel, AT25DF041A-MHF-T Datasheet - Page 12

• Manufacturer Part Number: AT25DF041A-MHF-T
• Description: IC FLASH 4MBIT 50MHZ 8UDFN
• Manufacturer: Atmel

Specifications of AT25DF041A-MHF-T

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 4M (2048 pages x 256 bytes)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-UDFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-3.
Figure 8-4.
8.3
12
SO
CS
SI
Seqeuntial Program Mode
Note: Each transition
Block Erase
AT25DF041A
SO
CS
Command
SI
Opcode A
Seqeuntial Program Mode
HIGH-IMPEDANCE
Note: Each transition
Sequential Program Mode – Status Register Polling
Sequential Program Mode – Waiting Maximum Byte Program Time
First Address to Program
Command
23-16
Opcode A
HIGH-IMPEDANCE
A
First Address to Program
15-8
23-16
A block of 4, 32, or 64 Kbytes can be erased (all bits set to the logical “1” state) in a single oper-
ation by using one of three different opcodes for the Block Erase command. An opcode of 20h is
used for a 4-Kbyte erase, an opcode of 52h is used for a 32-Kbyte erase, and an opcode of D8h
is used for a 64-Kbyte erase. Before a Block Erase command can be started, the Write Enable
command must have been previously issued to the device to set the WEL bit of the Status Reg-
ister to a logical “1” state.
To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h,
52h or D8h) must be clocked into the device. After the opcode has been clocked in, the three
address bytes specifying an address within the 4-, 32-, or 64-Kbyte block to be erased must be
clocked in. Any additional data clocked into the device will be ignored. When the CS pin is deas-
serted, the device will erase the appropriate block. The erasing of the block is internally self-
timed and should take place in a time of t
Since the Block Erase command erases a region of bytes, the lower order address bits do not
need to be decoded by the device. Therefore, for a 4-Kbyte erase, address bits A11 - A0 will be
ignored by the device and their values can be either a logical “1” or “0”. For a 32-Kbyte erase,
address bits A14 - A0 will be ignored, and for a 64-Kbyte erase, address bits A15 - A0 will be
ignored by the device. Despite the lower order address bits not being decoded by the device, the
complete three address bytes must still be clocked into the device before the CS pin is deas-
serted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);
otherwise, the device will abort the operation and no erase operation will be performed.
A
7-0
shown for SI represents one byte (8 bits)
A
15-8
Data
A
7-0
Status Register Read
shown for SI represents one byte (8 bits)
Command
Data
05h
STATUS REGISTER
DATA
t
BP
Seqeuntial Program Mode
Seqeuntial Program Mode
Command
Opcode
Command
Opcode
Data
Data
BLKE
05h
STATUS REGISTER
t
.
BP
Seqeuntial Program Mode
DATA
Seqeuntial Program Mode
Command
Opcode
Command
Opcode
Data
Data
Write Disable
t
Command
BP
04h
Write Disable
Command
04h
05h
STATUS REGISTER
3668D–DFLASH–9/08
DATA