AD9508/PCBZ Analog Devices, AD9508/PCBZ Datasheet - Page 30

• Manufacturer Part Number: AD9508/PCBZ
• Description: Clock & Timer Development Tools 1
• Manufacturer: Analog Devices
• Type: Clock Buffersr

Specifications of AD9508/PCBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD9508
• Frequency: 250 MHz, 1.65 GHz
• Operating Supply Voltage: 6 V
• Description/function: High performance 1
• Interface Type: I2C, SPI, USB
• Factory Pack Quantity: 1

Data Transfer Process
The master initiates a data transfer by asserting a start condition,
which indicates that a data stream follows. All I2C slave devices
connected to the serial bus respond to the start condition.
The master then sends an 8-bit address byte over the SDA line,
consisting of a 7-bit slave address (MSB first) plus an R/
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 =
write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by sending an acknowledge bit. All other
devices on the bus remain idle while the selected device waits
for data to be read from or written to it. If the R/
master (transmitter) writes to the slave device (receiver). If the
R/
(transmitter). The format for these commands is described in
the Data Transfer Format section.
Data is then sent over the serial bus in the format of nine clock
pulses: one data byte (eight bits) from either master (write mode)
or slave (read mode) followed by an acknowledge bit from the
receiving device. The number of bytes that can be transmitted
per transfer is unrestricted. In write mode, the first two data
AD9508
A
W
E
A
bit is 1, the master (receiver) reads from the slave device
SDA
SDA
SCL
SCL
S
S
SDA
SCL
MSB
MSB
1
1
START CONDITION
S
2
2
Figure 57. Data Transfer Process (Master Write Mode, Two-Byte Transfer)
3 TO 7
3 TO 7
W
A
E
A
bit is 0, the
Figure 55. Start and Stop Conditions
W
A
8
8
Figure 56. Acknowledge Bit
E
A
bit.
SLAVE RECEIVER
SLAVE RECEIVER
Rev. A | Page 30 of 40
ACK FROM
ACK FROM
9
9
bytes immediately after the slave address byte serve as the inter-
nal memory (control registers) address bytes, with the high
address byte first. This addressing scheme gives a memory
address of up to 2
two memory address bytes are register data that are written
to or read from the control registers. In read mode, the data
bytes after the slave address byte are register data that are
written to or read from the control registers.
When all data bytes are read or written, stop conditions are
established. In write mode, the master (transmitter) asserts a
stop condition to end data transfer during the 10
following the acknowledge bit for the last data byte from the
slave device (receiver). In read mode, the master device (receiver)
receives the last data byte from the slave device (transmitter)
but does not pull SDA low during the ninth clock pulse. This
condition is known as a no acknowledge bit. By receiving the no
acknowledge bit, the slave device knows that the data transfer is
finished and enters idle mode. The master then takes the data
line low during the low period before the 10
high during the 10
A start condition can be used in place of a stop condition.
Furthermore, a start or stop condition can occur at any time,
and partially transferred bytes are discarded.
1
1
2
2
16
3 TO 7
th
3 TO 7
− 1 = 65,535. The data bytes after these
clock pulse to assert a stop condition.
STOP CONDITION
P
8
8
SLAVE RECEIVER
SLAVE RECEIVER
ACK FROM
ACK FROM
9
9
th
clock pulse and
Data Sheet
10
10
P
P
th
clock pulse