AT25DF161-SH-B Atmel, AT25DF161-SH-B Datasheet - Page 29

• Manufacturer Part Number: AT25DF161-SH-B
• Description: IC FLASH 16MBIT 100MHZ 8SOIC
• Manufacturer: Atmel

Specifications of AT25DF161-SH-B

• Format - Memory: FLASH
• Memory Type: DataFLASH
• Memory Size: 16M (2M x 8)
• Speed: 100MHz
• Interface: SPI, RapidS
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Density: 16Mb
• Access Time (max): 5ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC EIAJ
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 2M
• Supply Current: 19mA
• Mounting: Surface Mount
• Pin Count: 8
• Mounting Style: SMD/SMT
• Memory Configuration: 8192 Pages X 256 Bytes
• Clock Frequency: 100MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3687E–DFLASH–11/10
10.5
The Program OTP Security Register command utilizes the internal 256-buffer for processing. Therefore, the contents of
the buffer will be altered from its previous state when this command is issued.
Figure 10-4. Program OTP Security Register
Read OTP Security Register
The OTP Security Register can be sequentially read in a similar fashion to the Read Array operation up to the maximum
clock frequency specified by f
77h must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to
specify the starting address location of the first byte to read within the OTP Security Register. Following the three address
bytes, two dummy bytes must be clocked into the device before data can be output.
After the three address bytes and the dummy bytes have been clocked in, additional clock cycles will result in OTP Security
Register data being output on the SO pin. When the last byte (00007Fh) of the OTP Security Register has been read, the
device will continue reading back at the beginning of the register (000000h). No delays will be incurred when wrapping
around from the end of the register to the beginning of the register.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can
be deasserted at any time and does not require that a full byte of data be read.
Figure 10-5. Read OTP Security Register
SCK
SCK
SO
CS
SO
CS
SI
SI
MAX
. To read the OTP Security Register, the CS pin must first be asserted and the opcode of
Atmel AT25DF161
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