EVAL-AD5171DBZ Analog Devices, EVAL-AD5171DBZ Datasheet - Page 4

• Manufacturer Part Number: EVAL-AD5171DBZ
• Description: Digital Potentiometer Development Tools EVALUATION BOARD I.C.
• Manufacturer: Analog Devices
• Series: AD5171r

Specifications of EVAL-AD5171DBZ

• Rohs: yes
• Product: Evaluation Boards
• Tool Is For Evaluation Of: AD5171
• Resistance: 5 kOhms/10 kOhms/50 kOhms/100 kOhms
• Operating Supply Voltage: 5.5 V
• Interface Type: I2C
• Maximum Operating Temperature: + 125 C
• Factory Pack Quantity: 1
• For Use With: Sim DAC Web Tool

AD5171
Parameter
DYNAMIC CHARACTERISTICS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Typical specifications represent average readings at 25°C and V
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
V
INL and DNL are measured at V
of ±1 LSB maximum are guaranteed monotonic operating conditions.
The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
Guaranteed by design; not subject to production test.
The minimum voltage requirement on the V
to V
up resistors.
Guaranteed by design; not subject to production test.
Different from operating power supply; power supply for OTP is used one time only.
Different from operating current; supply current for OTP lasts approximately 400 ms for one-time need only.
See Figure 24 for the energy plot during the OTP program.
P
Bandwidth, noise, and settling time depend on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
All dynamic characteristics use V
bandwidth. The highest R value results in the minimum overall power consumption.
AB
–3 dB Bandwidth
Total Harmonic Distortion
Adjustment Settling Time
Power-Up Settling Time After Fuses Blown
Resistor Noise Voltage
DISS
= V
DD
is calculated from (I
. However, care must be taken to ensure that the minimum V
DD
, Wiper (V
W
) = no connect.
DD
× V
DD
W
). CMOS logic level inputs result in minimum power dissipation.
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
8, 13, 14
DD
= 5 V.
IH
is 0.7 V × V
DD
. For example, V
Symbol
BW_5k
BW_10k
BW_50k
BW_100k
THD
t
t
e
S1
S2
N_WB
DD
= 5 V.
IH
is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-
Rev. D | Page 4 of 24
IH
minimum = 3.5 V when V
Conditions
R
R
R
R
V
V
V
V
V
V
R
code = 0x20
R
code = 0x20
AB
AB
AB
AB
A
B
A
B
A
B
AB
AB
= 1 V rms, R
= 0 V dc, f = 1 kHz
= 5 V ± 1 LSB error band,
= 0 V, measured at V
= 5 V ±1 LSB error band,
= 0 V, measured at V
= 5 kΩ, code = 0x20
= 10 kΩ, code = 0x20
= 50 kΩ, code = 0x20
= 100 kΩ, code = 0x20
= 5 kΩ, f = 1 kHz,
= 10 kΩ, f = 1 kHz,
AB
= 10 kΩ,
DD
= 5 V. It is typical for the SCL and SDA resistors to be pulled up
W
W
A
Min
= V
DD
and V
Typ
1500
600
110
60
0.05
5
5
8
12
B
= 0 V. DNL specification limits
1
Max
Unit
kHz
kHz
kHz
kHz
%
μs
μs
nV/√Hz
nV/√Hz