25LC512-E/SN Microchip Technology, 25LC512-E/SN Datasheet - Page 14

• Manufacturer Part Number: 25LC512-E/SN
• Description: IC EEPROM 512KBIT 20MHZ 8SOIC
• Manufacturer: Microchip Technology

Specifications of 25LC512-E/SN

• Memory Size: 512K (64K x 8)
• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Speed: 20MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Memory Configuration: 64K X 8
• Ic Interface Type: Serial, SPI
• Clock Frequency: 20MHz
• Access Time: 25ns
• Supply Voltage Range: 2.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25LC512
2.8
The PAGE ERASE instruction will erase all bits (FFh)
inside the given page. A Write Enable (WREN) instruc-
tion must be given prior to attempting a PAGE ERASE.
This is done by setting CS low and then clocking out
the proper instruction into the 25LC512. After all eight
bits of the instruction are transmitted, the CS must be
brought high to set the write enable latch.
The PAGE ERASE instruction is entered by driving CS
low, followed by the instruction code (Figure 2-8) and
two address bytes. Any address inside the page to be
erased is a valid address.
FIGURE 2-8:
DS22065C-page 14
PAGE ERASE
SCK
SO
CS
SI
PAGE ERASE SEQUENCE
0
0
1
1
0
Instruction
2
0
3
0
4
0
5
High-Impedance
1
6
0
7
15 14 13 12
8
CS must then be driven high after the last bit of the
address or the PAGE ERASE will not execute. Once
the CS is driven high the self-timed PAGE
cycle is started. The WIP bit in the STATUS register
can be read to determine when the PAGE ERASE cycle
is complete.
If a PAGE ERASE instruction is given to an address
that has been protected by the Block Protect bits (BP0,
BP1) then the sequence will be aborted and no erase
will occur.
9 10 11
16-bit Address
21 22 23
2
 2010 Microchip Technology Inc.
1
0
ERASE