UPMU-M3L1xLCD-B-EK Silicon Labs, UPMU-M3L1xLCD-B-EK Datasheet - Page 48

• Manufacturer Part Number: UPMU-M3L1xLCD-B-EK
• Description: Daughter Cards & OEM Boards UDP SiM3L1xx MCU Card (with LCD)
• Manufacturer: Silicon Labs

Specifications of UPMU-M3L1xLCD-B-EK

• Product: MCU Cards
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Description/function: MCU Card (with Static LCD) to use with UDP Motherboard
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Tool Is For Evaluation Of: SiM3L1xx
• For Use With: SiM3L1xx

SiM3L1xx
4.7.3. SPI (SPI0, SPI1)
SPI is a 3- or 4-wire communication interface that includes a clock, input data, output data, and an optional select
signal.
The SPI0 and SPI1 modules include the following features:
In addition, the SPI modules include several features to support autonomous DMA transfers:
SPI1 is on fixed pins and supports additional flow control options using a fixed input (SPI1CTS). Neither SPI1 nor
the flow control input are on the crossbar.
4.7.4. I2C (I2C0)
The I2C interface is a two-wire, bi-directional serial bus. The clock and data signals operate in open-drain mode
with external pull-ups to support automatic bus arbitration.
Reads and writes to the interface are byte oriented with the I2C interface autonomously controlling the serial
transfer of the data. Data can be transferred at up to 1/8th of the APB clock as a master or slave, which can be
faster than allowed by the I2C specification, depending on the clock source used. A method of extending the clock-
low duration is available to accommodate devices with different speed capabilities on the same bus.
The I2C interface may operate as a master and/or slave, and may function on a bus with multiple masters. The I2C
provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic, and start/
stop control and generation.
The I2C0 module includes the following features:
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Multiple loop-back modes supported.
Multi-processor communications support.
Operates at 9600, 4800, 2400, or 1200 baud in Power Mode 8.
Supports 3- or 4-wire master or slave modes.
Supports up to 10 MHz clock in master mode and 5 MHz clock in slave mode.
Support for all clock phase and slave select (NSS) polarity modes.
16-bit programmable clock rate.
Programmable MSB-first or LSB-first shifting.
8-byte FIFO buffers for both transmit and receive data paths to support high speed transfers.
Support for multiple masters on the same data lines.
Hardware NSS control.
Programmable FIFO threshold levels.
Configurable FIFO data widths.
Master or slave hardware flow control for the MISO and MOSI signals.
Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds.
Can operate down to APB clock divided by 32768 or up to APB clock divided by 8.
Support for master, slave, and multi-master modes.
Hardware synchronization and arbitration for multi-master mode.
Clock low extending (clock stretching) to interface with faster masters.
Hardware support for 7-bit slave and general call address recognition.
Firmware support for 10-bit slave address decoding.
Ability to disable all slave states.
Programmable clock high and low period.
Programmable data setup/hold times.
Spike suppression up to 2 times the APB period.
Rev 0.5